File a10_pcie_registers.h

#define BUFFER_STATUS_REGISTER_R `0x1b`

#define CLK_LINK_0_REGISTER_W `0x30`

#define CLK_LINK_1_REGISTER_W `0x31`

#define CLK_LINK_2_REGISTER_W `0x32`

#define CLK_LINK_3_REGISTER_W `0x33`

#define CLK_LINK_REST_REGISTER_W `0x34`

#define CNT_FEB_MERGE_TIMEOUT_R `0x25`

#define CNT_PLL_156_REGISTER_R `0x0a`

#define CNT_PLL_250_REGISTER_R `0x0b`

#define DATAGENERATOR_BIT_DMA_HALFFUL_MODE `5`

#define DATAGENERATOR_BIT_ENABLE `0`

#define DATAGENERATOR_BIT_ENABLE_FIBRE `2`

#define DATAGENERATOR_BIT_ENABLE_PIXEL `1`

#define DATAGENERATOR_BIT_ENABLE_TEST `4`

#define DATAGENERATOR_BIT_ENABLE_TILE `3`

#define DATAGENERATOR_DIVIDER_REGISTER_W `0x03`

#define DATAGENERATOR_FRACCOUNT_RANGE_HI `15`

#define DATAGENERATOR_FRACCOUNT_RANGE_LOW `8`

#define DATAGENERATOR_NFIBRE_RANGE_HI `23`

#define DATAGENERATOR_NFIBRE_RANGE_LOW `16`

#define DATAGENERATOR_NPIXEL_RANGE_HI `15`

#define DATAGENERATOR_NPIXEL_RANGE_LOW `8`

#define DATAGENERATOR_NTILE_RANGE_HI `31`

#define DATAGENERATOR_NTILE_RANGE_LOW `24`

#define DATAGENERATOR_REGISTER_W `0x02`

#define DATA_LINK_MASK_REGISTER_W `0x0b`

#define DATA_REQ_A_W `0x23`

#define DATA_REQ_B_W `0x24`

#define DATA_TSBLOCKS_R `0x28`

#define DATA_TSBLOCK_DONE_W `0x25`

#define DDR_BIT_CAL_FAIL `1`

#define DDR_BIT_CAL_SUCCESS `0`

#define DDR_BIT_COUNTERTEST_A `1`

#define DDR_BIT_COUNTERTEST_B `17`

#define DDR_BIT_ENABLE_A `0`

#define DDR_BIT_ENABLE_B `16`

#define DDR_BIT_READY `3`

#define DDR_BIT_RESET_N `2`

#define DDR_BIT_TEST_DONE `6`

#define DDR_BIT_TEST_READING `5`

#define DDR_BIT_TEST_WRITING `4`

#define DDR_CLK_CNT_R `0x30`

#define DDR_CONTROL_W `0x21`

#define DDR_ERR_R `0x27`

#define DDR_STATUS_R `0x26`

#define DIPSWITCH_RANGE_HI `1`

#define DIPSWITCH_RANGE_LOW `0`

#define DMA2_BIT_ADDR_WRITE_ENABLE `18`

#define DMA2_BIT_ENABLE `16`

#define DMA2_BIT_ENABLE_INTERRUPTS `19`

#define DMA2_BIT_NOW `17`

#define DMA2_CTRL_ADDR_HI_REGISTER_W `0x37`

#define DMA2_CTRL_ADDR_LOW_REGISTER_W `0x36`

#define DMA2_DATA_ADDR_HI_REGISTER_R `0x3e`

#define DMA2_DATA_ADDR_LOW_REGISTER_R `0x3d`

#define DMA2_NUM_ADDRESSES_RANGE_HI `27`

#define DMA2_NUM_ADDRESSES_RANGE_LOW `16`

#define DMA2_NUM_PAGES_REGISTER_R `0x3f`

#define DMA2_STATUS_REGISTER_R `0x3c`

#define DMA_BIT_ADDR_WRITE_ENABLE `2`

#define DMA_BIT_ENABLE `0`

#define DMA_BIT_ENABLE_INTERRUPTS `3`

#define DMA_BIT_NOW `1`

#define DMA_CNT_WORDS_REGISTER_R `0x32`

#define DMA_CONTROL_COUNTER_RANGE_HI `15`

#define DMA_CONTROL_COUNTER_RANGE_LOW `0`

#define DMA_CONTROL_W `0x05`

#define DMA_CTRL_ADDR_HI_REGISTER_W `0x3a`

#define DMA_CTRL_ADDR_LOW_REGISTER_W `0x39`

#define DMA_DATA_ADDR_HI_REGISTER_R `0x3a`

#define DMA_DATA_ADDR_HI_REGISTER_W `0x3c`

#define DMA_DATA_ADDR_LOW_REGISTER_R `0x39`

#define DMA_DATA_ADDR_LOW_REGISTER_W `0x3b`

#define DMA_ENDEVENT_REGISTER_R `0x16`

#define DMA_HALFFUL_REGISTER_R `0x14`

#define DMA_NOTENDEVENT_REGISTER_R `0x17`

#define DMA_NOTHALFFUL_REGISTER_R `0x15`

#define DMA_NUM_ADDRESSES_RANGE_HI `11`

#define DMA_NUM_ADDRESSES_RANGE_LOW `0`

#define DMA_NUM_ADDRESSES_REGISTER_W `0x3e`

#define DMA_NUM_PAGES_RANGE_HI `19`

#define DMA_NUM_PAGES_RANGE_LOW `0`

#define DMA_NUM_PAGES_REGISTER_R `0x3b`

#define DMA_RAM_LOCATION_NUM_PAGES_REGISTER_W `0x3d`

#define DMA_RAM_LOCATION_RANGE_HI `31`

#define DMA_RAM_LOCATION_RANGE_LOW `20`

#define DMA_REGISTER_W `0x38`

#define DMA_SLOW_DOWN_REGISTER_W `0x06`

#define DMA_STATUS_R `0x11`

#define DMA_STATUS_REGISTER_R `0x38`

#define EVENT2COUNTER64_REGISTER_R `0x08`

#define EVENTCOUNTER64_REGISTER_R `0x03`

#define EVENTCOUNTER_REGISTER_R `0x02`

#define EVENT_BUILD_CNT_EVENT_DMA_R `0x1f`

#define EVENT_BUILD_IDLE_NOT_HEADER_R `0x1d`

#define EVENT_BUILD_SKIP_EVENT_DMA_R `0x1e`

#define EVENT_BUILD_STATUS_REGISTER_R `0x1c`

#define EVENT_BUILD_TAG_FIFO_FULL_R `0x20`

#define FARM_CTL_REGISTER_W `0x28`

#define FARM_DATA_TYPE_ADDR_RANGE_HI `1`

#define FARM_DATA_TYPE_ADDR_RANGE_LOW `0`

#define FARM_DATA_TYPE_REGISTER_W `0x17`

#define FARM_EVENT_ID_ADDR_RANGE_HI `17`

#define FARM_EVENT_ID_ADDR_RANGE_LOW `2`

#define FARM_EVENT_ID_REGISTER_W `0x2b`

#define FARM_GPU_EVENT_PADDING_W `0x2d`

#define FARM_GPU_EVENT_SIZE_W `0x2c`

#define FARM_ID_REGISTER_W `0x26`

#define FARM_LINK_MASK_REGISTER_W `0x22`

#define FARM_READOUT_STATE_REGISTER_W `0x16`

#define FARM_REQ_EVENTS_W `0x27`

#define FARM_SERIAL_NUMBER_W `0x2e`

#define FEB_ENABLE_REGISTER_W `0x0a`

#define GET_DATAGENERATOR_BIT_DMA_HALFFUL_MODE (
    REG
) `((REG >> 5) & 0x1)`

#define GET_DATAGENERATOR_BIT_ENABLE (
    REG
) `((REG >> 0) & 0x1)`

#define GET_DATAGENERATOR_BIT_ENABLE_FIBRE (
    REG
) `((REG >> 2) & 0x1)`

#define GET_DATAGENERATOR_BIT_ENABLE_PIXEL (
    REG
) `((REG >> 1) & 0x1)`

#define GET_DATAGENERATOR_BIT_ENABLE_TEST (
    REG
) `((REG >> 4) & 0x1)`

#define GET_DATAGENERATOR_BIT_ENABLE_TILE (
    REG
) `((REG >> 3) & 0x1)`

#define GET_DATAGENERATOR_FRACCOUNT_RANGE (
    REG
) `((REG >> 8) & 0xff)`

#define GET_DATAGENERATOR_NFIBRE_RANGE (
    REG
) `((REG >> 16) & 0xff)`

#define GET_DATAGENERATOR_NPIXEL_RANGE (
    REG
) `((REG >> 8) & 0xff)`

#define GET_DATAGENERATOR_NTILE_RANGE (
    REG
) `((REG >> 24) & 0xff)`

#define GET_DDR_BIT_CAL_FAIL (
    REG
) `((REG >> 1) & 0x1)`

#define GET_DDR_BIT_CAL_SUCCESS (
    REG
) `((REG >> 0) & 0x1)`

#define GET_DDR_BIT_COUNTERTEST_A (
    REG
) `((REG >> 1) & 0x1)`

#define GET_DDR_BIT_COUNTERTEST_B (
    REG
) `((REG >> 17) & 0x1)`

#define GET_DDR_BIT_ENABLE_A (
    REG
) `((REG >> 0) & 0x1)`

#define GET_DDR_BIT_ENABLE_B (
    REG
) `((REG >> 16) & 0x1)`

#define GET_DDR_BIT_READY (
    REG
) `((REG >> 3) & 0x1)`

#define GET_DDR_BIT_RESET_N (
    REG
) `((REG >> 2) & 0x1)`

#define GET_DDR_BIT_TEST_DONE (
    REG
) `((REG >> 6) & 0x1)`

#define GET_DDR_BIT_TEST_READING (
    REG
) `((REG >> 5) & 0x1)`

#define GET_DDR_BIT_TEST_WRITING (
    REG
) `((REG >> 4) & 0x1)`

#define GET_DIPSWITCH_RANGE (
    REG
) `((REG >> 0) & 0x3)`

#define GET_DMA2_BIT_ADDR_WRITE_ENABLE (
    REG
) `((REG >> 18) & 0x1)`

#define GET_DMA2_BIT_ENABLE (
    REG
) `((REG >> 16) & 0x1)`

#define GET_DMA2_BIT_ENABLE_INTERRUPTS (
    REG
) `((REG >> 19) & 0x1)`

#define GET_DMA2_BIT_NOW (
    REG
) `((REG >> 17) & 0x1)`

#define GET_DMA2_NUM_ADDRESSES_RANGE (
    REG
) `((REG >> 16) & 0xfff)`

#define GET_DMA_BIT_ADDR_WRITE_ENABLE (
    REG
) `((REG >> 2) & 0x1)`

#define GET_DMA_BIT_ENABLE (
    REG
) `((REG >> 0) & 0x1)`

#define GET_DMA_BIT_ENABLE_INTERRUPTS (
    REG
) `((REG >> 3) & 0x1)`

#define GET_DMA_BIT_NOW (
    REG
) `((REG >> 1) & 0x1)`

#define GET_DMA_CONTROL_COUNTER_RANGE (
    REG
) `((REG >> 0) & 0xffff)`

#define GET_DMA_NUM_ADDRESSES_RANGE (
    REG
) `((REG >> 0) & 0xfff)`

#define GET_DMA_NUM_PAGES_RANGE (
    REG
) `((REG >> 0) & 0xfffff)`

#define GET_DMA_RAM_LOCATION_RANGE (
    REG
) `((REG >> 20) & 0xfff)`

#define GET_FARM_DATA_TYPE_ADDR_RANGE (
    REG
) `((REG >> 0) & 0x3)`

#define GET_FARM_EVENT_ID_ADDR_RANGE (
    REG
) `((REG >> 2) & 0xffff)`

#define GET_LINK_TEST_BIT_ENABLE (
    REG
) `((REG >> 0) & 0x1)`

#define GET_N_DMA_WORDS_REGISTER_W `0x0c`

#define GET_N_GPU_EVENTS_REGISTER_W `0x35`

#define GET_RESET_BIT_ALL (
    REG
) `((REG >> 0) & 0x1)`

#define GET_RESET_BIT_DATAFIFO (
    REG
) `((REG >> 5) & 0x1)`

#define GET_RESET_BIT_DATAFLOW (
    REG
) `((REG >> 20) & 0x1)`

#define GET_RESET_BIT_DATAGEN (
    REG
) `((REG >> 1) & 0x1)`

#define GET_RESET_BIT_DATA_PATH (
    REG
) `((REG >> 22) & 0x1)`

#define GET_RESET_BIT_DDR (
    REG
) `((REG >> 19) & 0x1)`

#define GET_RESET_BIT_DMA_EVAL (
    REG
) `((REG >> 14) & 0x1)`

#define GET_RESET_BIT_EVENT_COUNTER (
    REG
) `((REG >> 13) & 0x1)`

#define GET_RESET_BIT_FARM_BLOCK (
    REG
) `((REG >> 28) & 0x1)`

#define GET_RESET_BIT_FARM_DATA_PATH (
    REG
) `((REG >> 23) & 0x1)`

#define GET_RESET_BIT_FARM_STREAM_MERGER (
    REG
) `((REG >> 24) & 0x1)`

#define GET_RESET_BIT_FARM_TIME_MERGER (
    REG
) `((REG >> 25) & 0x1)`

#define GET_RESET_BIT_FIFOPLL (
    REG
) `((REG >> 6) & 0x1)`

#define GET_RESET_BIT_GLOBAL_TS (
    REG
) `((REG >> 27) & 0x1)`

#define GET_RESET_BIT_LINK_LOCKED (
    REG
) `((REG >> 26) & 0x1)`

#define GET_RESET_BIT_LINK_MERGER (
    REG
) `((REG >> 21) & 0x1)`

#define GET_RESET_BIT_LINK_TEST (
    REG
) `((REG >> 15) & 0x1)`

#define GET_RESET_BIT_NIOS (
    REG
) `((REG >> 18) & 0x1)`

#define GET_RESET_BIT_PCIE (
    REG
) `((REG >> 31) & 0x1)`

#define GET_RESET_BIT_PCIE_APPL (
    REG
) `((REG >> 12) & 0x1)`

#define GET_RESET_BIT_PCIE_LOCAL (
    REG
) `((REG >> 9) & 0x1)`

#define GET_RESET_BIT_RECEIVER (
    REG
) `((REG >> 4) & 0x1)`

#define GET_RESET_BIT_RUN_END_ACK (
    REG
) `((REG >> 17) & 0x1)`

#define GET_RESET_BIT_RUN_START_ACK (
    REG
) `((REG >> 16) & 0x1)`

#define GET_RESET_BIT_SC_MAIN (
    REG
) `((REG >> 8) & 0x1)`

#define GET_RESET_BIT_SC_SECONDARY (
    REG
) `((REG >> 7) & 0x1)`

#define GET_RESET_BIT_SWB_COUNTERS (
    REG
) `((REG >> 29) & 0x1)`

#define GET_RESET_BIT_SWB_STREAM_MERGER (
    REG
) `((REG >> 2) & 0x1)`

#define GET_RESET_BIT_SWB_TIME_MERGER (
    REG
) `((REG >> 3) & 0x1)`

#define GET_RESET_BIT_TOP_PROC (
    REG
) `((REG >> 10) & 0x1)`

#define GET_RESET_LINK_COMMAND_RANGE (
    REG
) `((REG >> 0) & 0xff)`

#define GET_RESET_LINK_FEB_RANGE (
    REG
) `((REG >> 29) & 0x7)`

#define GET_REST_0_RANGE (
    REG
) `((REG >> 0) & 0xff)`

#define GET_REST_1_RANGE (
    REG
) `((REG >> 8) & 0xff)`

#define GET_REST_2_RANGE (
    REG
) `((REG >> 16) & 0xff)`

#define GET_REST_3_RANGE (
    REG
) `((REG >> 24) & 0xff)`

#define GET_SWB_LOOKUP_CTRL_ADDR_RANGE (
    REG
) `((REG >> 0) & 0x7f)`

#define GET_SWB_LOOKUP_CTRL_COMMAND_RANGE (
    REG
) `((REG >> 7) & 0x3)`

#define GET_SWB_LOOKUP_CTRL_VALUE_RANGE (
    REG
) `((REG >> 9) & 0x3fff)`

#define GET_USE_BIT_ALL (
    REG
) `((REG >> 12) & 0x1)`

#define GET_USE_BIT_DDR (
    REG
) `((REG >> 11) & 0x1)`

#define GET_USE_BIT_FARM (
    REG
) `((REG >> 5) & 0x1)`

#define GET_USE_BIT_FEB_SYNC (
    REG
) `((REG >> 19) & 0x1)`

#define GET_USE_BIT_GENERIC (
    REG
) `((REG >> 18) & 0x1)`

#define GET_USE_BIT_GEN_LINK (
    REG
) `((REG >> 0) & 0x1)`

#define GET_USE_BIT_GEN_MERGER (
    REG
) `((REG >> 4) & 0x1)`

#define GET_USE_BIT_HEAD_SUPPRESS (
    REG
) `((REG >> 15) & 0x1)`

#define GET_USE_BIT_INJECTION (
    REG
) `((REG >> 16) & 0x1)`

#define GET_USE_BIT_MERGER (
    REG
) `((REG >> 2) & 0x1)`

#define GET_USE_BIT_PIXEL_DS (
    REG
) `((REG >> 8) & 0x1)`

#define GET_USE_BIT_PIXEL_ONLY (
    REG
) `((REG >> 0) & 0x1)`

#define GET_USE_BIT_PIXEL_US (
    REG
) `((REG >> 7) & 0x1)`

#define GET_USE_BIT_SCIFI (
    REG
) `((REG >> 9) & 0x1)`

#define GET_USE_BIT_SCIFI_ONLY (
    REG
) `((REG >> 1) & 0x1)`

#define GET_USE_BIT_SEND_TIME (
    REG
) `((REG >> 20) & 0x1)`

#define GET_USE_BIT_STREAM (
    REG
) `((REG >> 1) & 0x1)`

#define GET_USE_BIT_SUBHDR_SUPPRESS (
    REG
) `((REG >> 14) & 0x1)`

#define GET_USE_BIT_TEST (
    REG
) `((REG >> 6) & 0x1)`

#define GET_USE_BIT_TEST_DATA (
    REG
) `((REG >> 13) & 0x1)`

#define GET_USE_BIT_TEST_ERROR (
    REG
) `((REG >> 10) & 0x1)`

#define GET_USE_BIT_WRITE_BUFFER_INJECTION (
    REG
) `((REG >> 17) & 0x1)`

#define GET_VERSION_RANGE (
    REG
) `((REG >> 0) & 0xfffffff)`

#define GET_XCVR_CTRL_CH_RANGE (
    REG
) `((REG >> 16) & 0x3f)`

#define GET_XCVR_CTRL_REG_RANGE (
    REG
) `((REG >> 0) & 0xff)`

#define GLOBAL_TS_HIGH_REGISTER_R `0x2b`

#define GLOBAL_TS_LOW_REGISTER_R `0x2a`

#define INADDR32_R `0x09`

#define INADDR32_W `0x10`

#define INJECTION_WAIT_W `0x18`

#define LED_REGISTER_W `0x00`

#define LINK_LOCKED_HIGH_REGISTER_R `0x37`

#define LINK_LOCKED_LOW_REGISTER_R `0x36`

#define LINK_TEST_BIT_ENABLE `0`

#define LINK_TEST_REGISTER_W `0x07`

#define MEM_WRITEADDR_HIGH_REGISTER_R `0x07`

#define MEM_WRITEADDR_LOW_REGISTER_R `0x06`

#define PLL_LOCKED_REGISTER_R `0x12`

#define PLL_REGISTER_R `0x00`

#define RESET_BIT_ALL `0`

#define RESET_BIT_DATAFIFO `5`

#define RESET_BIT_DATAFLOW `20`

#define RESET_BIT_DATAGEN `1`

#define RESET_BIT_DATA_PATH `22`

#define RESET_BIT_DDR `19`

#define RESET_BIT_DMA_EVAL `14`

#define RESET_BIT_EVENT_COUNTER `13`

#define RESET_BIT_FARM_BLOCK `28`

#define RESET_BIT_FARM_DATA_PATH `23`

#define RESET_BIT_FARM_STREAM_MERGER `24`

#define RESET_BIT_FARM_TIME_MERGER `25`

#define RESET_BIT_FIFOPLL `6`

#define RESET_BIT_GLOBAL_TS `27`

#define RESET_BIT_LINK_LOCKED `26`

#define RESET_BIT_LINK_MERGER `21`

#define RESET_BIT_LINK_TEST `15`

#define RESET_BIT_NIOS `18`

#define RESET_BIT_PCIE `31`

#define RESET_BIT_PCIE_APPL `12`

#define RESET_BIT_PCIE_LOCAL `9`

#define RESET_BIT_RECEIVER `4`

#define RESET_BIT_RUN_END_ACK `17`

#define RESET_BIT_RUN_START_ACK `16`

#define RESET_BIT_SC_MAIN `8`

#define RESET_BIT_SC_SECONDARY `7`

#define RESET_BIT_SWB_COUNTERS `29`

#define RESET_BIT_SWB_STREAM_MERGER `2`

#define RESET_BIT_SWB_TIME_MERGER `3`

#define RESET_BIT_TOP_PROC `10`

#define RESET_LINK_COMMAND_RANGE_HI `7`

#define RESET_LINK_COMMAND_RANGE_LOW `0`

#define RESET_LINK_CTL_REGISTER_W `0x29`

#define RESET_LINK_FEB_RANGE_HI `31`

#define RESET_LINK_FEB_RANGE_LOW `29`

#define RESET_LINK_RUN_NUMBER_REGISTER_W `0x2a`

#define RESET_LINK_STATUS_REGISTER_R `0x35`

#define RESET_REGISTER_W `0x01`

#define REST_0_RANGE_HI `7`

#define REST_0_RANGE_LOW `0`

#define REST_1_RANGE_HI `15`

#define REST_1_RANGE_LOW `8`

#define REST_2_RANGE_HI `23`

#define REST_2_RANGE_LOW `16`

#define REST_3_RANGE_HI `31`

#define REST_3_RANGE_LOW `24`

#define RUN_NR_ACK_REGISTER_R `0x18`

#define RUN_NR_ADDR_REGISTER_W `0x09`

#define RUN_NR_REGISTER_R `0x19`

#define RUN_NR_REGISTER_W `0x08`

#define RUN_STOP_ACK_REGISTER_R `0x1a`

#define SC_MAIN_ENABLE_REGISTER_W `0x0d`

#define SC_MAIN_LENGTH_REGISTER_W `0x0e`

#define SC_MAIN_STATUS_REGISTER_R `0x29`

#define SC_STATE_REGISTER_R `0x31`

#define SERIAL_NUM_REGISTER_R `0x2c`

#define SET_DATAGENERATOR_BIT_DMA_HALFFUL_MODE (
    REG
) `((1 << 5) | REG)`

#define SET_DATAGENERATOR_BIT_ENABLE (
    REG
) `((1 << 0) | REG)`

#define SET_DATAGENERATOR_BIT_ENABLE_FIBRE (
    REG
) `((1 << 2) | REG)`

#define SET_DATAGENERATOR_BIT_ENABLE_PIXEL (
    REG
) `((1 << 1) | REG)`

#define SET_DATAGENERATOR_BIT_ENABLE_TEST (
    REG
) `((1 << 4) | REG)`

#define SET_DATAGENERATOR_BIT_ENABLE_TILE (
    REG
) `((1 << 3) | REG)`

#define SET_DATAGENERATOR_FRACCOUNT_RANGE (
    REG,
    VAL
) `((REG & (~(0xff << 8))) | ((VAL & 0xff) << 8))`

#define SET_DATAGENERATOR_NFIBRE_RANGE (
    REG,
    VAL
) `((REG & (~(0xff << 16))) | ((VAL & 0xff) << 16))`

#define SET_DATAGENERATOR_NPIXEL_RANGE (
    REG,
    VAL
) `((REG & (~(0xff << 8))) | ((VAL & 0xff) << 8))`

#define SET_DATAGENERATOR_NTILE_RANGE (
    REG,
    VAL
) `((REG & (~(0xff << 24))) | ((VAL & 0xff) << 24))`

#define SET_DDR_BIT_CAL_FAIL (
    REG
) `((1 << 1) | REG)`

#define SET_DDR_BIT_CAL_SUCCESS (
    REG
) `((1 << 0) | REG)`

#define SET_DDR_BIT_COUNTERTEST_A (
    REG
) `((1 << 1) | REG)`

#define SET_DDR_BIT_COUNTERTEST_B (
    REG
) `((1 << 17) | REG)`

#define SET_DDR_BIT_ENABLE_A (
    REG
) `((1 << 0) | REG)`