| LED_REGISTER_W |
REG: 0x00 |
USED TO CHANGE LEDS ON THE BOARDS |
FARM |
WRITE-REG |
| RESET_REGISTER_W |
REG: 0x01 |
RESET REGISTER |
ALL |
WRITE-REG |
| RESET_BIT_ALL |
BIT: 0 |
RESET BIT TO RESET ALL |
ALL |
- |
| RESET_BIT_DATAGEN |
BIT: 1 |
RESET BIT FOR THE DATAGENERATOR WHICH IS GENERATING THE LINK DATA FROM FEBS |
SWB |
- |
| RESET_BIT_SWB_STREAM_MERGER |
BIT: 2 |
RESET ROUND ROBIN MERGER |
SWB |
- |
| RESET_BIT_SWB_TIME_MERGER |
BIT: 3 |
RESET TIME MERGER |
SWB |
- |
| RESET_BIT_RECEIVER |
BIT: 4 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_DATAFIFO |
BIT: 5 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_FIFOPLL |
BIT: 6 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_SC_SECONDARY |
BIT: 7 |
RESET BIT FOR THE SLOWCONTROL SECONDARY |
SWB |
- |
| RESET_BIT_SC_MAIN |
BIT: 8 |
RESET BIT FOR THE SLOWCONTROL MAIN |
SWB |
- |
| RESET_BIT_PCIE_LOCAL |
BIT: 9 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_TOP_PROC |
BIT: 10 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_PCIE_APPL |
BIT: 12 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_EVENT_COUNTER |
BIT: 13 |
RESET BIT FOR THE SWB_DATA_DEMERGER |
SWB |
- |
| RESET_BIT_DMA_EVAL |
BIT: 14 |
RESET BIT FOR DMA EVALUATIONG / MONITORING FOR PCIE 0 |
ALL |
- |
| RESET_BIT_LINK_TEST |
BIT: 15 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_RUN_START_ACK |
BIT: 16 |
REST BIT FOR SEEING THE RUN ACK IN RUN_CONTROL |
SWB |
- |
| RESET_BIT_RUN_END_ACK |
BIT: 17 |
REST BIT FOR SEEING THE RUN END IN RUN_CONTROL |
SWB |
- |
| RESET_BIT_NIOS |
BIT: 18 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_DDR |
BIT: 19 |
RESET BIT FOR DDR CONTROL ENTITIE |
FARM |
- |
| RESET_BIT_DATAFLOW |
BIT: 20 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_LINK_MERGER |
BIT: 21 |
NOT USED AT THE MOMENT |
ALL |
- |
| RESET_BIT_DATA_PATH |
BIT: 22 |
RESET BIT FOR THE DATA PATH |
SWB |
- |
| RESET_BIT_FARM_DATA_PATH |
BIT: 23 |
RESET BIT FOR THE DATA PATH |
FARM |
- |
| RESET_BIT_FARM_STREAM_MERGER |
BIT: 24 |
RESET BIT FOR FARM STREAM MERGER |
FARM |
- |
| RESET_BIT_FARM_TIME_MERGER |
BIT: 25 |
RESET BIT FOR FARM TIME MERGER |
FARM |
- |
| RESET_BIT_LINK_LOCKED |
BIT: 26 |
RESET BIT FOR LINK LOCKED BIT |
SWB/FARM |
- |
| RESET_BIT_GLOBAL_TS |
BIT: 27 |
RESET BIT FOR GLOBAL TIME COUNTER |
SWB/FARM |
- |
| RESET_BIT_FARM_BLOCK |
BIT: 28 |
RESET BIT FOR THE DATA PATH |
FARM |
- |
| RESET_BIT_SWB_COUNTERS |
BIT: 29 |
RESET BIT FOR THE COUNTERS ON THE SWB |
SWB |
- |
| RESET_BIT_PCIE |
BIT: 31 |
NOT USED AT THE MOMENT |
ALL |
- |
| DATAGENERATOR_REGISTER_W |
REG: 0x02 |
REGISTER TO CONTROL THE DATAGENERATOR WHICH IS GENERATING THE LINK DATA FROM FEBS |
SWB |
WRITE-REG |
| DATAGENERATOR_BIT_ENABLE |
BIT: 0 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_BIT_ENABLE_PIXEL |
BIT: 1 |
BIT TO ENABLE PIXEL DATA |
SWB |
- |
| DATAGENERATOR_BIT_ENABLE_FIBRE |
BIT: 2 |
BIT TO ENABLE FIBRE DATA |
SWB |
- |
| DATAGENERATOR_BIT_ENABLE_TILE |
BIT: 3 |
BIT TO ENABLE TILE DATA |
SWB |
- |
| DATAGENERATOR_BIT_ENABLE_TEST |
BIT: 4 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_BIT_DMA_HALFFUL_MODE |
BIT: 5 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_FRACCOUNT_RANGE |
RANGE: 15 DOWNTO 8 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_NPIXEL_RANGE |
RANGE: 15 DOWNTO 8 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_NFIBRE_RANGE |
RANGE: 23 DOWNTO 16 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_NTILE_RANGE |
RANGE: 31 DOWNTO 24 |
NOT USED AT THE MOMENT |
SWB |
- |
| DATAGENERATOR_DIVIDER_REGISTER_W |
REG: 0x03 |
REGISTER TO SLOW DOWN THE DATAGENERATOR WHICH IS GENERATING THE LINK DATA FROM FEBS |
SWB |
WRITE-REG |
| SWB_DATA_TYPE_REGISTER_W |
REG: 0x04 |
SET THE DIFFERENT DATA TYPES (6BITS) FOR THE DATA PATHS ON THE SWB BOARD |
SWB |
WRITE-REG |
| DMA_CONTROL_COUNTER_RANGE |
RANGE: 15 DOWNTO 0 |
NOT USED AT THE MOMENT |
ALL |
- |
| DMA_SLOW_DOWN_REGISTER_W |
REG: 0x06 |
NOT USED AT THE MOMENT |
ALL |
WRITE-REG |
| LINK_TEST_REGISTER_W |
REG: 0x07 |
NOT USED AT THE MOMENT |
ALL |
WRITE-REG |
| LINK_TEST_BIT_ENABLE |
BIT: 0 |
NOT USED AT THE MOMENT |
ALL |
- |
| RUN_NR_REGISTER_W |
REG: 0x08 |
REGISTER TO WRITE THE CURRENT RUN NUMBER |
SWB |
WRITE-REG |
| RUN_NR_ADDR_REGISTER_W |
REG: 0x09 |
ASK FOR RUN NUMBER OF FEB WITH THIS ADDR |
SWB |
WRITE-REG |
| FEB_ENABLE_REGISTER_W |
REG: 0x0A |
ENABLE REGISTER FOR FEBS FOR RUN CONTROL AND SLOWCONTROL |
SWB |
WRITE-REG |
| DATA_LINK_MASK_REGISTER_W |
REG: 0x0B |
NOT USED AT THE MOMENT |
SWB |
WRITE-REG |
| GET_N_DMA_WORDS_REGISTER_W |
REG: 0x0C |
NUMBER OF REQUESTED WORDS WHICH WILL BE SEND VIA DMA |
SWB & FARM |
WRITE-REG |
| SC_MAIN_ENABLE_REGISTER_W |
REG: 0x0D |
REG THAT THE SLOWCONTROL MAIN ONLY STARTS ON A 0->1 TRANSITION |
SWB |
WRITE-REG |
| SC_MAIN_LENGTH_REGISTER_W |
REG: 0x0E |
LENGHT (15 DOWNTO 0) FOR SLOWCONTROL PACKAGE |
SWB |
WRITE-REG |
| SWB_GENERIC_MASK_REGISTER_W |
REG: 0x0F |
MASK GENERIC LINKS FOR DEV SETUP |
SWB |
WRITE-REG |
| SWB_LINK_MASK_PIXEL_REGISTER_W |
REG: 0x10 |
MASK PIXEL LINKS |
SWB |
WRITE-REG |
| SWB_LINK_MASK_SCIFI_REGISTER_W |
REG: 0x11 |
MASK SCIFI LINKS |
SWB |
WRITE-REG |
| SWB_LINK_MASK_TILES_REGISTER_W |
REG: 0x12 |
MASK TILE LINKS |
SWB |
WRITE-REG |
| SWB_READOUT_STATE_REGISTER_W |
REG: 0x13 |
READOUT STATE |
SWB |
WRITE-REG |
| USE_BIT_GEN_LINK |
BIT: 0 |
READOUT STATE WHERE LINK DATA IS GENERATED (FOR DEBUGGING) |
SWB & FARM |
- |
| USE_BIT_STREAM |
BIT: 1 |
READOUT STATE WHERE LINK DATA IS READ OUT IN ROUND-ROBIN |
SWB & FARM |
- |
| USE_BIT_MERGER |
BIT: 2 |
READOUT STATE WHERE LINK DATA IS TIME ALIGNED (TREE) |
SWB & FARM |
- |
| USE_BIT_GEN_MERGER |
BIT: 4 |
READOUT STATE WHERE THE TIME ALIGNED DATA IS GENERATED (FOR DEBUGGING) |
SWB & FARM |
- |
| USE_BIT_FARM |
BIT: 5 |
READOUT STATE WHERE THE DATA IS SEND TO THE FARM (1) ELSE (0) IT IS READOUT VIA DMA ON THE SWB |
SWB & FARM |
- |
| USE_BIT_TEST |
BIT: 6 |
NOT USED AT THE MOMENT |
SWB & FARM |
- |
| USE_BIT_PIXEL_US |
BIT: 7 |
READOUT STATE TO ONLY READOUT US PIXEL DATA VIA DMA (FOR DEBUGGING) |
SWB & FARM |
- |
| USE_BIT_PIXEL_DS |
BIT: 8 |
READOUT STATE TO ONLY READOUT DS PIXEL DATA VIA DMA (FOR DEBUGGING) |
SWB & FARM |
- |
| USE_BIT_SCIFI |
BIT: 9 |
READOUT STATE TO ONLY READOUT SCIFI DATA VIA DMA (FOR DEBUGGING) |
SWB & FARM |
- |
| USE_BIT_TEST_ERROR |
BIT: 10 |
READOUT STATE FOR TESTING AN ERROR HANDLING IN THE TIME MERGER USING GENERATED DATA |
SWB & FARM |
- |
| USE_BIT_DDR |
BIT: 11 |
READOUT STATE FOR USING THE DDR MEMORY |
FARM |
- |
| USE_BIT_ALL |
BIT: 12 |
READOUT STATE TO ONLY READOUT ALL DATA IN ROUND ROBIN VIA DMA (FOR DEBUGGING) |
SWB |
- |
| USE_BIT_TEST_DATA |
BIT: 13 |
READOUT STATE WHERE LINK DATA IS REAL DATA FROM MEM FILE (FOR SIMULATION |
SWB |
- |
| USE_BIT_SUBHDR_SUPPRESS |
BIT: 14 |
READOUT STATE WHERE SUBHEADERS ARE SUPPRESSED |
SWB |
- |
| USE_BIT_HEAD_SUPPRESS |
BIT: 15 |
READOUT STATE WHERE HEADERS ARE SUPPRESSED |
SWB |
- |
| USE_BIT_INJECTION |
BIT: 16 |
READOUT STATE TO INJECTED DATA |
SWB & FARM |
- |
| USE_BIT_WRITE_BUFFER_INJECTION |
BIT: 17 |
READOUT STATE TO INJECTED DATA |
SWB & FARM |
WRITE-REG |
| USE_BIT_GENERIC |
BIT: 18 |
READOUT STATE TO ONLY READOUT GENERIC DATA VIA DMA (FOR DEBUGGING) |
SWB |
- |
| USE_BIT_FEB_SYNC |
BIT: 19 |
SETTING THIS BIT TO ONE ENABLES THE SYNC OF THE FEB DATA |
SWB |
- |
| SWB_READOUT_LINK_REGISTER_W |
REG: 0x14 |
NOT USED AT THE MOMENT |
SWB & FARM |
WRITE-REG |
| SWB_COUNTER_REGISTER_W |
REG: 0x15 |
ADDR REGISTER TO READOUT COUNTER VALUES FROM THE SWB, TO HAVE MORE INFORMATION ABOUT THE COUNTER LOOK AT A10_COUNTER.MD |
SWB |
WRITE-REG |
| FARM_READOUT_STATE_REGISTER_W |
REG: 0x; |
READOUT STATE |
FARM |
WRITE-REG |
| FARM_DATA_TYPE_REGISTER_W |
REG: 0x17 |
DATA TYPE FOR READOUT |
FARM |
WRITE-REG |
| FARM_DATA_TYPE_ADDR_RANGE |
RANGE: 1 DOWNTO 0 |
DATA TYPE: "00" = PIXEL, "01" = SCIFI, "10" = TILES |
FARM |
- |
| FARM_EVENT_ID_ADDR_RANGE |
RANGE: 17 DOWNTO 2 |
MIDAS EVENT ID |
FARM |
- |
| SWB_SUBHEAD_SUPPRESS_REGISTER_W |
REG: 0x19 |
SUBHEADER SUPPRESSION PER LINK |
SWB |
WRITE-REG |
| SWB_HEAD_SUPPRESS_REGISTER_W |
REG: 0x1A |
HEADER SUPPRESSION PER LINK |
SWB |
WRITE-REG |
| SWB_ZERO_HISTOS_REGISTER_W |
REG: 0x1B |
TODO |
SWB |
WRITE-REG |
| SWB_HISTO_ADDR_REGISTER_W |
REG: 0x1C |
TODO |
SWB |
WRITE-REG |
| SWB_HISTO_CHIP_SELECT_REGISTER_W |
REG: 0x1D |
TODO |
SWB |
WRITE-REG |
| SWB_HISTO_LINK_SELECT_REGISTER_W |
REG: 0x1E |
TODO |
SWB |
WRITE-REG |
| SWB_LOOKUP_CTRL_REGISTER_W |
REG: 0x1F |
CTRL REGISTER TO WRITE CHIP LOOKUP |
SWB |
WRITE-REG |
| SWB_LOOKUP_DS_CTRL_REGISTER_W |
REG: 0x20 |
CTRL REGISTER TO WRITE CHIP LOOKUP |
SWB |
WRITE-REG |
| SWB_LOOKUP_CTRL_ADDR_RANGE |
RANGE: 6 DOWNTO 0 |
ADDR FOR THE RAM |
SWB |
- |
| SWB_LOOKUP_CTRL_COMMAND_RANGE |
RANGE: 8 DOWNTO 7 |
COMMAND FOR THE STATE MACHINE |
SWB |
- |
| SWB_LOOKUP_CTRL_VALUE_RANGE |
RANGE: 22 DOWNTO 9 |
LOOKUP VALUE |
SWB |
- |
| DDR_BIT_ENABLE_A |
BIT: 0 |
ENABLE STATEMACHINE OF DDR-A |
FARM |
- |
| DDR_BIT_COUNTERTEST_A |
BIT: 1 |
ENABLE COUNTER TEST (1) OR DATAFLOW (0) OF DDR-A |
FARM |
- |
| DDR_COUNTERSEL_RANGE_A |
RANGE: 15 DOWNTO 14 |
"01" -> GET POSERR_REG, "10" -> GET COUNTERR_REG ELSE CUR TIME COUNTER WRITTEN TO DDR |
FARM |
- |
| DDR_RANGE_A |
RANGE: 15 DOWNTO 0 |
RANGE FOR DDR A |
FARM |
- |
| DDR_BIT_ENABLE_B |
BIT: 16 |
ENABLE STATEMACHINE OF DDR-B |
FARM |
- |
| DDR_BIT_COUNTERTEST_B |
BIT: 17 |
ENABLE COUNTER TEST (1) OR DATAFLOW (0) OF DDR-B |
FARM |
- |
| DDR_COUNTERSEL_RANGE_B |
RANGE: 31 DOWNTO 30 |
"01" -> GET POSERR_REG, "10" -> GET COUNTERR_REG ELSE CUR TIME COUNTER WRITTEN TO DDR |
FARM |
- |
| DDR_RANGE_B |
RANGE: 31 DOWNTO 16 |
RANGE FOR DDR B |
FARM |
- |
| FARM_LINK_MASK_REGISTER_W |
REG: 0x22 |
MASK FARM LINKS |
FARM |
WRITE-REG |
| FARM_ID_REGISTER_W |
REG: 0x26 |
FARM ID WRITTEN TO THE RESERVED FILED OF THE MIDAS BANK |
FARM |
WRITE-REG |
| FARM_EVENT_ID_REGISTER_W |
REG: 0x2B |
SET MIDAS EVENT ID (15 DOWNTO 0) AND TRIGGER MASK (31 DOWNTO 16) |
FARM |
WRITE-REG |
| XCVR_CTRL_REGISTER_W |
REG: 0x2F |
SELECT INTERNAL XCVR-REGISTER |
SWB |
WRITE-REG |
| XCVR_CTRL_CH_RANGE |
RANGE: 21 DOWNTO 16 |
XCVR CHANNEL SELECTOR |
SWB |
- |
| XCVR_CTRL_REG_RANGE |
RANGE: 7 DOWNTO 0 |
XCVR REGISTER SELECTOR |
SWB |
- |
| GET_N_GPU_EVENTS_REGISTER_W |
REG: 0x35 |
NUMBER OF REQUESTED GPU EVENTS WHICH WILL BE SEND VIA DMA |
FARM |
WRITE-REG |