| MP_CTRL_COMBINED_START_REGISTER_W |
REG: 0x0400 |
USED TO SEND COMBINED CONFIG DATA TO THE MUPIX, CHIP ID ENCODED IN ADDR AS REGADDR + CHIPID |
MP_FEB |
WRITE-REG |
| MP_CTRL_TDAC_START_REGISTER_W |
REG: 0x0430 |
USED TO SEND TDAC TO THE MUPIX, CHIP ID ENCODED IN ADDR AS REGADDR + CHIPID |
MP_FEB |
WRITE-REG |
| MP_CTRL_CHIP_SELECT1_REGISTER_W |
REG: 0x0460 |
USED TO SPECIFY THE CHIP ID IN CASE OF DIRECT SPI OR DIRECT REGISTER CONFIGURATION |
MP_FEB |
WRITE-REG |
| MP_CTRL_CHIP_SELECT2_REGISTER_W |
REG: 0x0461 |
USED TO SPECIFY THE CHIP ID IN CASE OF DIRECT SPI OR DIRECT REGISTER CONFIGURATION |
MP_FEB |
WRITE-REG |
| MP_CTRL_BIAS_REGISTER_W |
REG: 0x0462 |
IF YOU WANT TO WRITE THE MUPIX BIAS REG ONLY, SEND DATA HERE |
MP_FEB |
WRITE-REG |
| MP_CTRL_CONF_REGISTER_W |
REG: 0x0463 |
IF YOU WANT TO WRITE THE MUPIX CONF REG ONLY, SEND DATA HERE |
MP_FEB |
WRITE-REG |
| MP_CTRL_VDAC_REGISTER_W |
REG: 0x0464 |
IF YOU WANT TO WRITE THE MUPIX VDAC REG ONLY, SEND DATA HERE |
MP_FEB |
WRITE-REG |
| MP_CTRL_SLOW_DOWN_REGISTER_W |
REG: 0x0465 |
DIVISION FACTOR FOR THE MUPIX SPI CLK |
MP_FEB |
WRITE-REG |
| MP_CTRL_SPI_BUSY_REGISTER_R |
REG: 0x0466 |
INDICATES IF THE MUPIX SPI IS BUSY, DO NOT SEND NEW DATA |
MP_FEB |
- |
| MP_CTRL_DIRECT_SPI_ENABLE_REGISTER_W |
REG: 0x0467 |
ENABLE DIRECT SPI CONFIGURATION MODE FOR MUPIX |
MP_FEB |
WRITE-REG |
| MP_CTRL_SPI_ENABLE_REGISTER_W |
REG: 0x0468 |
ENABLE SPI CONFIGURATION MODE FOR MUPIX (DIRECT SPI NEEDS TO BE DISABLED IN THIS CASE) |
MP_FEB |
WRITE-REG |
| MP_CTRL_DIRECT_SPI_BUSY_REGISTER_R |
REG: 0x0469 |
CONTAINS 1 BIT FOR EACH SPI BUS, 1 IF BUSY |
MP_FEB |
- |
| MP_CTRL_DIRECT_SPI_START_REGISTER_W |
REG: 0x046A |
REGISTER FOR DIRECT SPI CONFIGURATION MODE, NEEDS TO BE ENABLED FIRST |
MP_FEB |
WRITE-REG |
| MP_CTRL_DIRECT_SPI_CHIP_M_LOW_REGISTER_W |
REG: 0x0480 |
REGISTER TO SET THE CHIP MASK FOR THE LOWER 32 LINKS WHEN USING DIRECT SPI MODE |
MP_FEB |
WRITE-REG |
| MP_CTRL_DIRECT_SPI_CHIP_M_HIGH_REGISTER_W |
REG: 0x0481 |
REGISTER TO SET THE CHIP MASK FOR THE HIGHER 32 LINKS WHEN USING DIRECT SPI MODE |
MP_FEB |
WRITE-REG |
| MP_CTRL_RESET_REGISTER_W |
REG: 0x04A0 |
WRITE TO THIS REG TRIGGERS A 1 CYCLE MP CTRL RESET |
MP_FEB |
WRITE-REG |
| MP_CTRL_RUN_TEST_REGISTER_W |
REG: 0x04A1 |
WRITE TO THIS REG TRIGGERS WRITE OF A TDAC TEST PATTERN |
MP_FEB |
WRITE-REG |
| MP_CTRL_N_FREE_PAGES_REGISTER_R |
REG: 0x04A2 |
NUMBER OF FREE TDAC PAGES |
MP_FEB |
- |
| MP_CTRL_TESTRAM_RDATA_REGISTER_R |
REG: 0x04A3 |
NUMBER OF FREE TDAC PAGES |
MP_FEB |
- |
| MP_CTRL_TESTRAM_WADDR_REGISTER_W |
REG: 0x04A4 |
NUMBER OF FREE TDAC PAGES |
MP_FEB |
WRITE-REG |
| MP_CTRL_TESTRAM_RADDR_REGISTER_W |
REG: 0x04A5 |
NUMBER OF FREE TDAC PAGES |
MP_FEB |
WRITE-REG |
| MP_CTRL_TESTRAM_WDATA_REGISTER_W |
REG: 0x04A6 |
NUMBER OF FREE TDAC PAGES |
MP_FEB |
WRITE-REG |
| MP_CTRL_SLOW_CLK_SHIFT_REGISTER_W |
REG: 0x04A7 |
SHIFT OF THE SLOW CLOCK VS RESET |
MP_FEB |
WRITE-REG |
| MP_CTRL_SIN_INVERT_REGISTER_W |
REG: 0x04A8 |
INVERT SIN |
MP_FEB |
WRITE-REG |
| MP_CTRL_EXT_CMD_START_REGISTER_W |
REG: 0x0800 |
START OF REGISTERS TO SEND DIRECT COMMANDS TO MUPIX SENSORS, MAINLY FOR READBACK FUNCTIONALITY. 2 ADDRESSES FOR EACH CHIP SINCE A COMMAND HAS 64 BITS, COMMAND TRIGGERS AUTOMATICALLY ONCE WRITTEN HERE |
MP_FEB |
WRITE-REG |
| MP_READOUT_MODE_REGISTER_W |
REG: 0x1300 |
TO BE REMOVED |
MP_FEB |
WRITE-REG |
| CHIP_ID_MODE_RANGE |
RANGE: 5 DOWNTO 4 |
BITS TO SELECT DIFFERENT CHIP ID NUMBERING MODES (NOT IN USE) |
MP_FEB |
- |
| TOT_MODE_RANGE |
RANGE: 8 DOWNTO 6 |
BITS TO SELECT DIFFERENT TOT CALCULATION MODES (DEFAULT IS TO SEND TS2 AS TOT, NOT IN USE) |
MP_FEB |
- |
| MP_LVDS_LINK_MASK_REGISTER_W |
REG: 0x1301 |
MASKING OF LVDS CONNECTIONS |
FEB |
WRITE-REG |
| MP_LVDS_LINK_MASK2_REGISTER_W |
REG: 0x1302 |
MASKING OF LVDS CONNECTIONS |
FEB |
WRITE-REG |
| MP_DATA_GEN_CONTROL_REGISTER_W |
REG: 0x1303 |
CONTROLS THE MUPIX DATA GENERATOR |
MP_FEB |
WRITE-REG |
| MP_DATA_GEN_HIT_P_RANGE |
RANGE: 3 DOWNTO 0 |
GENERATOR HIT OUTPUT PROBABILITY, 1/(2^(MP_DATA_GEN_HIT_P_RANGE+1)) FOR EACH CYCLE WHERE A HIT COULD BE SEND |
MP_FEB |
- |
| MP_DATA_BYPASS_SELECT_REGISTER_W |
REG: 0x1305 |
BYPASS THE MUPIX SOTER AND PUT INPUT TO_INTEGER(THISREG) DIRECTLY ON OPTICAL LINK (IMPLEMENTED BUT NOT CONNECTED IN TOP) |
MP_FEB |
WRITE-REG |
| MP_TS_HISTO_SELECT_REGISTER_W |
REG: 0x1306 |
NOT IN USE |
MP_FEB |
WRITE-REG |
| MP_TS_HISTO_LINK_SELECT_RANGE |
RANGE: 15 DOWNTO 0 |
NOT IN USE |
MP_FEB |
- |
| MP_TS_HISTO_N_SAMPLE_RANGE |
RANGE: 31 DOWNTO 16 |
NOT IN USE |
MP_FEB |
- |
| MP_LAST_SORTER_HIT_REGISTER_R |
REG: 0x1307 |
REGISTER THAT CONTAINS THE LAST MUPIX HIT OF THE SORTER OUTPUT |
MP_FEB |
- |
| MP_SORTER_INJECT_REGISTER_W |
REG: 0x1308 |
USED TO INJECT SINGLE HITS AT THE SORTER INPUTS |
MP_FEB |
WRITE-REG |
| MP_SORTER_INJECT_SELECT_RANGE |
RANGE: 7 DOWNTO 4 |
INPUT OF THE SORTER TO INJECT TO |
MP_FEB |
- |
| MP_CHIP_UNPACKER_CNT_REGISTER_R |
REG: 0x1309 |
COUNTER OUTPUT FROM THE UNPACKER |
MP_FEB |
- |
| MP_CHIP_UNPACKER_CNT_REGISTER_W |
REG: 0x130A |
REGISTER TO SELECT THE CHIP/LINK OF THE UNPACKER COUNTER AND THE COUNTER TO READ FROM |
MP_FEB |
WRITE-REG |
| MP_CHIP_UNPACKER_CNT_SELECT_RANGE |
RANGE: 7 DOWNTO 0 |
SELECT THE LVDS LINKT TO READOUT (0-35) |
MP_FEB |
- |
| MP_CNT_UNPACKER_SELECT_RANGE |
RANGE: 10 DOWNTO 8 |
SELECT THE COUNTER FROM THIS LINK TO READOUT (0-7) |
MP_FEB |
- |
| MP_HIT_ENA_CNT_SORTER_IN_REGISTER_R |
REG: 0x130B |
HIT ENABLE COUNTER AT THE SORTER INPUT |
MP_FEB |
- |
| MP_HIT_ENA_CNT_SORTER_SELECT_REGISTER_W |
REG: 0x130C |
REGISTER TO SELECT THE LINK FOR THE SORTER INPUT HIN ENA COUNTER |
MP_FEB |
WRITE-REG |
| MP_HIT_ENA_CNT_SORTER_OUT_REGISTER_R |
REG: 0x130D |
HIT COUNTER AT SORTER OUTPUT |
MP_FEB |
- |
| MP_RESET_LVDS_N_REGISTER_W |
REG: 0x130F |
RESET REGISTER FOR MUPIX LVDS RX |
MP_FEB |
WRITE-REG |
| MP_USE_ARRIVAL_TIME1_REGISTER_W |
REG: 0x1310 |
USE HIT ARRIVAL TIME INSTEAD OF TIMESTAMP FROM MUPIX (LOWER 32 CHIPS) |
MP_FEB |
WRITE-REG |
| MP_USE_ARRIVAL_TIME2_REGISTER_W |
REG: 0x1311 |
USE HIT ARRIVAL TIME INSTEAD OF TIMESTAMP FROM MUPIX (UPPDER 4 CHIPS) |
MP_FEB |
WRITE-REG |
| MP_TRIGGER0_REGISTER_R |
REG: 0x1312 |
TRIGGER0 |
MP_FEB |
- |
| MP_TRIGGER1_REGISTER_R |
REG: 0x1313 |
TRIGGER1 |
MP_FEB |
- |
| MP_TRIGGER0_REG_REGISTER_R |
REG: 0x1314 |
PREV-TRIGGER0 |
MP_FEB |
- |
| MP_TRIGGER1_REG_REGISTER_R |
REG: 0x1315 |
PREV-TRIGGER1 |
MP_FEB |
- |
| MP_LVDS_INVERT_0_REGISTER_W |
REG: 0x; |
INVERTING LVDS LINES |
FEB |
WRITE-REG |
| MP_LVDS_INVERT_1_REGISTER_W |
REG: 0x1317 |
INVERTING LVDS LINES |
FEB |
WRITE-REG |
| MP_IS_A_0_REGISTER_R |
REG: 0x1318 |
CHECK IF LINK IS AN A LINK |
FEB |
- |
| MP_IS_A_1_REGISTER_R |
REG: 0x1319 |
CHECK IF LINK IS AN A LINK |
FEB |
- |
| MP_IS_B_0_REGISTER_R |
REG: 0x1320 |
CHECK IF LINK IS AN B LINK |
FEB |
- |
| MP_IS_B_1_REGISTER_R |
REG: 0x1321 |
CHECK IF LINK IS AN B LINK |
FEB |
- |
| MP_IS_C_0_REGISTER_R |
REG: 0x1322 |
CHECK IF LINK IS AN C LINK |
FEB |
- |
| MP_IS_C_1_REGISTER_R |
REG: 0x1323 |
CHECK IF LINK IS AN C LINK |
FEB |
- |
| MP_READBACK_FIFOS_START_REGISTER_R |
REG: 0x2000 |
FIFOS WHERE SLOWCONTROL FROM THE MUPIX SENSORS CAN BE READ BACK, INCLUDES ALSO THE ERROR SIGNALS, ADC VALUES ARE IN READBACK MEMS |
MP_FEB |
- |
| MP_READBACK_MEMS_START_REGISTER_R |
REG: 0x3000 |
MEMORIES WHERE ADC MEASUREMENTS FROM THE MUPIX SENSORS CAN BE READ |
MP_FEB |
- |
| MP_HIT_ARRIVAL_START_REGISTER_R |
REG: 0x1200 |
START OF PLL LOCK MONITOR BLOCK, 4 WORDS FOR EACH CHIP, HISTOGRAM LOWER BITS OF MUPIX ARRIVAL TIMESTAMP |
MP_FEB |
- |
| MP_SORTER_COUNTER_REGISTER_R |
REG: 0x1000 |
HIT COUNTERS IN THE SORTER, 40 32 BIT COUNTERS IN TOTAL. FOR THE INNER PIXEL FEBS: 12 COUNTERS WITH IN-TIME HITS PER CHIP, 12 COUNTERS WITH OUT-OF-TIME HITS PER CHIP, 12 COUNTERS WITH OVERFLOWS PER CHIP, A COUNTER WITH THE NUMBER OF OUTPUT HITS AND THE CURRENT CREDIT VALUE. THE LAST TWO COUNTERS ARE CURRENTLY RESERVED FOR FUTURE USE |
MP_FEB |
- |
| MP_SORTER_DELAY_REGISTER_W |
REG: 0x1028 |
MINIMUM ROUND-TRIP DELAY FROM SYNC RESET GOING OFF TO HIT WITH TS > 0 APPEARING AT SORTER INPUT IN 8 NS STEPS |
MP_FEB |
WRITE-REG |