| STATUS_REGISTER_R |
REG: 0xFC00 |
NOT IN USE |
FEB_ALL |
- |
| GIT_HASH_REGISTER_R |
REG: 0xFC01 |
CONTAINS THE GIT HASH OF USED FIRMWARE |
FEB_ALL |
- |
| FPGA_TYPE_REGISTER_R |
REG: 0xFC02 |
CONTAINS FPGA TYPE 111010: MUPIX, 111000 : MUTRIG |
FEB_ALL |
- |
| FPGA_ID_REGISTER_RW |
REG: 0xFC03 |
FGPA ID |
FEB_ALL |
- |
| CMD_LEN_REGISTER_RW |
REG: 0xFC04 |
LENGTH OF DATA TO READ IN A NIOS RPC CALL |
FEB_ALL |
- |
| CMD_OFFSET_REGISTER_RW |
REG: 0xFC05 |
POSITON OF THE DATA TO READ IN A NIOS RPC CALL |
FEB_ALL |
- |
| RUN_STATE_RESET_BYPASS_REGISTER_RW |
REG: 0xFC06 |
USED TO BYPASS THE RESET SYSTEM AND RUN WITHOUT A CLOCK BOX |
FEB_ALL |
- |
| RUN_STATE_RANGE |
RANGE: 31 DOWNTO 16 |
NOT IN USE |
FEB_ALL |
- |
| RESET_BYPASS_RANGE |
RANGE: 7 DOWNTO 0 |
NOT IN USE |
FEB_ALL |
- |
| RESET_BYPASS_BIT_REQUEST |
BIT: 8 |
SENDS A BYPASS RESET COMMAND |
FEB_ALL |
- |
| RESET_BYPASS_BIT_ENABLE |
BIT: 9 |
ENABLES THE USE OF THE RESET BYPASS |
FEB_ALL |
- |
| RESET_PAYLOAD_REGISTER_RW |
REG: 0xFC07 |
PAYLOAD FOR THE RESET BYPASS COMMANDS |
FEB_ALL |
- |
| RESET_OPTICAL_LINKS_REGISTER_RW |
REG: 0xFC08 |
RESET FIREFLY |
FEB_ALL |
- |
| RESET_PHASE_REGISTER_R |
REG: 0xFC09 |
PHASE BETWEEN RESET RX CLOCK AND GLOBAL CLK |
FEB_ALL |
- |
| MERGER_RATE_REGISTER_R |
REG: 0xFC0A |
OUTPUT RATE OF THE DATA MERGER |
FEB_ALL |
- |
| ARRIA_TEMP_REGISTER_RW |
REG: 0xFC10 |
ARRIAV INTERNAL TEMP SENSE |
FEB_ALL |
- |
| MAX10_ADC_0_1_REGISTER_R |
REG: 0xFC11 |
MAX10 ADC DATA |
FEB_ALL |
- |
| NONINCREMENTING_TEST_REGISTER_RW |
REG: 0xFC24 |
TESTING NONINCREMENTING READS/WRITES TO FIFO (NOT IN USE) |
FEB_ALL |
- |
| MAX10_VERSION_REGISTER_R |
REG: 0xFC25 |
GIT HASH OF THE MAX10 FIRMWARE |
FEB_ALL |
- |
| RUN_START_DENIAL_REGISTER_R |
REG: 0xFC2F |
REASON FOR DENIED RUN START ACK |
FEB_ALL |
- |
| RUN_NUMBER_REGISTER_R |
REG: 0xFC2F |
RUN NUMBER ON THE FEB |
FEB_ALL |
- |