File odb_setup.h
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#include "midas.h"
#include "odbxx.h"
#include "registers.h"
template <typename T, std::size_t N>
constexpr std::array<T, N> filled_array(const T& value) {
std::array<T, N> arr{};
arr.fill(value);
return arr;
}
// Map /Equipment/Quads/Settings
midas::odb settings = {
{"Readout",
{{"Datagen Divider", 1000},
{"Sorter Delay", filled_array<uint64_t, N_FEBS>(200)},
{"Software dummy", false},
{"Datagen Enable", false},
{"mask_n_generic", 0x0},
{"use_merger", false},
{"max_requested_words", 0x80000},
{"use_send_time", false},
{"HitRate", 0},
{"n_mevents", 10}}},
{"DAQ",
{
{"Commands",
{{"InitFEBs", false},
{"Load Firmware", false},
{"Firmware File", ""},
{"Firmware FEB ID", 0},
{"FirmwareLoadProgress", 0.0},
{"Reset SWB Counters", false},
{"Run Cycle FEB", false},
{"Configure injection", false},
{"Injection columns", 15},
{"Injection rows", 15},
{"Trigger injection", false},
{"Trigger injection loop", false},
{"Injection min column", 0},
{"Injection max column", 255},
{"Injection min rows", 0},
{"Injection max rows", 249},
{"Injection pulse duration", 0x3f0},
{"Number of pulses", 20},
{"Wait time between pulses (ms)", 10},
{"Full chip Injection", false},
{"MupixConfig", false},
{"MupixTDACConfig", false},
{"ResetASICs", false},
{"ADC Continuous Readout", false},
{"DataGenEnable", false},
{"DataGenSync", false},
{"DataGenDisable", false},
{"DataGenFullSteam", false},
{"DataGenRate", 0},
{"Reset FEB Counters", false},
{"debug_readout_feb", false},
{"MuTRiG",
{{"init_tmb", false}, //If set, initializes the TMBs. Resets when finished
{"module_power", false}, //Global power switch for the ASICs
{"module_power_mask", filled_array<bool, 2>(false) }, //Selects modules that will be powered (ASICs which will be powered)
{"temperatures_read", false},
{"temperature_IDs_read", false},
{"powermonitors_read", false},
{"tmbstatus_read", false},
{"override_power_moduleid", 0}, //selects module to which the override is applied
{"override_ana_power_mask", 0x0000}, //selects analog power domains to be enabled
{"override_dig_power_mask", 0x0000}, //selects digital power domains to be enabled
{"dummy_config", false},
{"dummy_data", false},
{"dummy_data_n", 200},
{"dummy_data_fast", false},
{"reset_datapath", false},
{"reset_asics", false},
{"reset_lvds", false},
{"reset_counters", false},
{"lapse_boundary", filled_array<uint16_t, 2>(0)},
{"lapse_delay", 0},
{"lapse_replace_latency", 0},
{"is_mutrig_3", 1},
{"resetskew", {0}},
{"energy_scale", 0},
{"energy_offset", 0},
{"MutrigConfig", false},
{"MutrigConfigAllOff", false},
{"TestPulsesTDC", false}
}},
}
},
{"Links",
{{"LVDSLinkMask", filled_array<uint64_t, N_FEBS>(0xFFFFFF)},
{"LVDSLinkInvert", filled_array<uint64_t, N_FEBS>(35434004481)},
{"ASICMask", filled_array<uint16_t, N_FEBS>(0xFF)},
{"FEBsActive", filled_array<bool, N_FEBS>(false)},
{"FEBsQuads", filled_array<bool, N_FEBS>(false)},
{"FEBsMutrig", filled_array<bool, N_FEBS>(false)},
{"Mapping", { 0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31}}}},
}
},
{"Config",
{
{"BIASDACS",
{// PLL
{"VNVCO", filled_array<uint32_t, N_CHIPS * N_FEBS>(23)},
{"VPVCO", filled_array<uint32_t, N_CHIPS * N_FEBS>(22)},
{"VNTimerDel", filled_array<uint32_t, N_CHIPS * N_FEBS>(20)},
{"VPTimerDel", filled_array<uint32_t, N_CHIPS * N_FEBS>(10)},
{"VPPump", filled_array<uint32_t, N_CHIPS * N_FEBS>(30)},
{"VNLVDSDel", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VNLVDS", filled_array<uint32_t, N_CHIPS * N_FEBS>(16)},
{"VPDcl", filled_array<uint32_t, N_CHIPS * N_FEBS>(30)},
{"VNDelPreEmp", filled_array<uint32_t, N_CHIPS * N_FEBS>(32)},
{"VPDelPreEmp", filled_array<uint32_t, N_CHIPS * N_FEBS>(32)},
{"VNDcl", filled_array<uint32_t, N_CHIPS * N_FEBS>(10)},
{"VNDelDcl", filled_array<uint32_t, N_CHIPS * N_FEBS>(32)},
{"VPDelDcl", filled_array<uint32_t, N_CHIPS * N_FEBS>(32)},
{"VNDelDclMux", filled_array<uint32_t, N_CHIPS * N_FEBS>(32)},
{"VPDelDclMux", filled_array<uint32_t, N_CHIPS * N_FEBS>(32)},
{"VNDel", filled_array<uint32_t, N_CHIPS * N_FEBS>(10)},
{"VNRegC", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
// Pixel
{"VNPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(10)},
{"VPLoadPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(5)},
{"VNFBPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(3)},
{"VNFollPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(5)},
{"VNOutPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(5)},
{"VPComp1", filled_array<uint32_t, N_CHIPS * N_FEBS>(5)},
{"VPComp2", filled_array<uint32_t, N_CHIPS * N_FEBS>(5)},
{"VNBiasPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"BLResDig", filled_array<uint32_t, N_CHIPS * N_FEBS>(6)},
{"BLResPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(6)},
{"VNPix2", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VNComp", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VNDAC", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VPDAC", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
// General
{"ThRes", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"BiasBlock_on", filled_array<uint32_t, N_CHIPS * N_FEBS>(5)},
{"Bandgap_on", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VPFoll", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VNHB", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)}
}
},
{"CONFDACS",
{{"TestOut", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"AlwaysEnable", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"En2thre", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"EnPLL", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"SelFast", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"count_sheep", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"NC1", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"disable_HB", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"conf_res_n", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"RO_res_n", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"Ser_res_n", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"Aur_res_n", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"NC2", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"Tune_Reg_L", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"NC3", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"Tune_Reg_R", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"NC4", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"SelSlow", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"SelEx", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"invert", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"slowdownlDColEnd", filled_array<uint32_t, N_CHIPS * N_FEBS>(7)},
{"EnSync_SC", filled_array<uint32_t, N_CHIPS * N_FEBS>(1)},
{"NC5", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"linksel", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"tsphase", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"sendcounter", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"resetckdivend", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"NC6", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"maxcycend", filled_array<uint32_t, N_CHIPS * N_FEBS>(63)},
{"slowdownend", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"timerend", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"ckdivend2", filled_array<uint32_t, N_CHIPS * N_FEBS>(31)},
{"ckdivend", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)}
}
},
{"VDACS",
{{"BLPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(60)},
{"ThHigh", filled_array<uint32_t, N_CHIPS * N_FEBS>(135)},
{"ThLow", filled_array<uint32_t, N_CHIPS * N_FEBS>(134)},
{"Baseline", filled_array<uint32_t, N_CHIPS * N_FEBS>(112)},
{"ref_Vss", filled_array<uint32_t, N_CHIPS * N_FEBS>(169)},
{"VCAL", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"ThPix", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"ThHigh2", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"ThLow2", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)},
{"VDAC1", filled_array<uint32_t, N_CHIPS * N_FEBS>(0)}
}
},
{"Nbits",
{// BIASDACS
{"VNTimerDel", 6},
{"VPTimerDel", 6},
{"VNDAC", 6},
{"VPFoll", 6},
{"VNComp", 6},
{"VNHB", 6},
{"VPComp2", 6},
{"VPPump", 6},
{"VNLVDSDel", 6},
{"VNLVDS", 6},
{"VNDcl", 6},
{"VPDcl", 6},
{"VNDelPreEmp", 6},
{"VPDelPreEmp", 6},
{"VNDelDcl", 6},
{"VPDelDcl", 6},
{"VNDelDclMux", 6},
{"VPDelDclMux", 6},
{"VNVCO", 6},
{"VPVCO", 6},
{"VNOutPix", 6},
{"VPLoadPix", 6},
{"VNBiasPix", 6},
{"BLResDig", 6},
{"VNPix2", 6},
{"VPDAC", 6},
{"VPComp1", 6},
{"VNDel", 6},
{"VNRegC", 6},
{"VNFollPix", 6},
{"VNFBPix", 6},
{"VNPix", 6},
{"ThRes", 6},
{"BLResPix", 6},
{"BiasBlock_on", 3},
{"Bandgap_on", 1},
// here all inverse?
// CONFDACS
{"SelFast", 1},
{"count_sheep", 1},
{"NC1", 5},
{"TestOut", 4},
{"disable_HB", 1},
{"conf_res_n", 1},
{"RO_res_n", 1},
{"Ser_res_n", 1},
{"Aur_res_n", 1},
{"NC2", 1},
{"Tune_Reg_L", 6},
{"NC3", 1},
{"Tune_Reg_R", 6},
{"AlwaysEnable", 1},
{"En2thre", 1},
{"NC4", 4},
{"EnPLL", 1},
{"SelSlow", 1},
{"SelEx", 1},
{"invert", 1},
{"slowdownlDColEnd", 5},
{"EnSync_SC", 1},
{"NC5", 3},
{"linksel", 2},
{"tsphase", 6},
{"sendcounter", 1},
{"resetckdivend", 4},
{"NC6", 2},
{"maxcycend", 6},
{"slowdownend", 4},
{"timerend", 4},
{"ckdivend2", 6},
{"ckdivend", 6},
// VDACS
{"VCAL", 8},
{"BLPix", 8},
{"ThPix", 8},
{"ThHigh", 8},
{"ThLow", 8},
{"ThHigh2", 8},
{"ThLow2", 8},
{"Baseline", 8},
{"VDAC1", 8},
{"ref_Vss", 8}
}
},
{"Inverted",
{// BIASDACS
{"VNTimerDel", false},
{"VPTimerDel", false},
{"VNDAC", false},
{"VPFoll", false},
{"VNComp", false},
{"VNHB", false},
{"VPComp2", false},
{"VPPump", false},
{"VNLVDSDel", false},
{"VNLVDS", false},
{"VNDcl", false},
{"VPDcl", false},
{"VNDelPreEmp", false},
{"VPDelPreEmp", false},
{"VNDelDcl", false},
{"VPDelDcl", false},
{"VNDelDclMux", false},
{"VPDelDclMux", false},
{"VNVCO", false},
{"VPVCO", false},
{"VNOutPix", false},
{"VPLoadPix", false},
{"VNBiasPix", false},
{"BLResDig", false},
{"VNPix2", false},
{"VPDAC", false},
{"VPComp1", false},
{"VNDel", false},
{"VNRegC", false},
{"VNFollPix", false},
{"VNFBPix", false},
{"VNPix", false},
{"ThRes", false},
{"BLResPix", false},
{"BiasBlock_on", false},
{"Bandgap_on", false},
// here all inverse?
// CONFDACS
{"SelFast", true},
{"count_sheep", true},
{"NC1", true},
{"TestOut", true},
{"disable_HB", true},
{"conf_res_n", true},
{"RO_res_n", true},
{"Ser_res_n", true},
{"Aur_res_n", true},
{"NC2", true},
{"Tune_Reg_L", true},
{"NC3", true},
{"Tune_Reg_R", true},
{"AlwaysEnable", true},
{"En2thre", true},
{"NC4", true},
{"EnPLL", true},
{"SelSlow", true},
{"SelEx", true},
{"invert", true},
{"slowdownlDColEnd", true},
{"EnSync_SC", true},
{"NC5", true},
{"linksel", true},
{"tsphase", true},
{"sendcounter", true},
{"resetckdivend", true},
{"NC6", true},
{"maxcycend", true},
{"slowdownend", true},
{"timerend", true},
{"ckdivend2", true},
{"ckdivend", true},
// VDACS
{"VCAL", true},
{"BLPix", true},
{"ThPix", true},
{"ThHigh", true},
{"ThLow", true},
{"ThHigh2", true},
{"ThLow2", true},
{"Baseline", true},
{"VDAC1", true},
{"ref_Vss", true}
}
},
{"TDACS",
{
{"TDACFILE", filled_array<std::string, N_CHIPS * N_FEBS>("tdacfile.bin")}
}
}
}
},
{"ConfigMuTRiG",
{
{"Global",
{
{"ext_trig_mode", false},
{"ext_trig_endtime_sign", false},
{"ext_trig_offset", 8},
{"ext_trig_endtime", 8},
{"gen_idle", true},
{"ms_debug", false},
{"tx_mode", 0},
{"sync_ch_rst", true},
{"disable_coarse", false},
{"pll_setcoarse", false},
{"pll_envomonitor", false},
{"pll_lol_dbg", false},
{"en_ch_evt_cnt", false}
}
},
{"TDCs",
{
{"ms_limits", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"ms_switch_sel", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vnpfc", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(8)},
{"vnpfc_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vnpfc_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vncnt", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(40)},
{"vncnt_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vncnt_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vnvcobuffer", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"vnvcobuffer_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"vnvcobuffer_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vnd2c", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(31)},
{"vnd2c_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vnd2c_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vnpcp", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(24)},
{"vnpcp_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vnpcp_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vnhitlogic", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(24)},
{"vnhitlogic_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vnhitlogic_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vncntbuffer", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(7)},
{"vncntbuffer_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vncntbuffer_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"vnvcodelay", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(22)},
{"vnvcodelay_offset", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"vnvcodelay_scale", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"latchbias", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(1800)},
{"amon_en", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"amon_dac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(63)},
{"dmon_select", filled_array<int32_t, N_MUTRIGS_PER_FEB * N_FEBS>(-1)},
{"dmon_sw", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"dmon_1_en", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"dmon_1_dac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(31)},
{"dmon_2_en", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"dmon_2_dac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(5)},
{"lvds_tx_vcm", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(160)},
{"lvds_tx_bias", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(5)},
{"coin_xbar_lower_rx_ena", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"coin_xbar_lower_tx_ena", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"coin_xbar_lower_tx_vdac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"coin_xbar_lower_tx_idac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"coin_xbar_upper_rx_ena", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"coin_xbar_upper_tx_ena", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"coin_xbar_upper_tx_vdac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"coin_xbar_upper_tx_idac", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"coin_mat_xbl", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"coin_mat_xbu", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"coin_wnd", filled_array<uint32_t, N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"dmon_sel_enable", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"dmon_sel", filled_array<bool, N_MUTRIGS_PER_FEB * N_FEBS>(0x1f)}
}
},
{"Channels",
{
{"mask", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"recv_all", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"tthresh", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(61)},
{"tthresh_sc", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"tthresh_offset", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"ethresh", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(185)},
{"ebias", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"sipm", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(20)},
{"inputbias", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(4)},
{"pole", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(15)},
{"pole_sc", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"ampcom", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(21)},
{"ampcom_sc", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(3)},
{"cml", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(8)},
{"cml_sc", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"amonctrl", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(0)},
{"comp_spi", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(2)},
{"tdctest_n", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"sswitch", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"delay", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"pole_en_n", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"energy_c_en", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"energy_r_en", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"cm_sensing_high_r", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"amon_en_n", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"edge", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(true)},
{"edge_cml", filled_array<bool, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(false)},
{"coin_mat", filled_array<uint32_t, NMUTRIGCHANNELS * N_MUTRIGS_PER_FEB * N_FEBS>(0)}
}
},
{"Nbits",
{// header
{"gen_idle", 1},
{"sync_ch_rst", 1},
{"ext_trig_mode", 1},
{"ext_trig_endtime_sign", 1},
{"ext_trig_offset", 4},
{"ext_trig_endtime", 4},
{"ms_limits", 5},
{"ms_switch_sel", 1},
{"ms_debug", 1},
{"tx_mode", 3},
{"pll_setcoarse", 1},
{"pll_envomonitor", 1},
{"disable_coarse", 1},
{"pll_lol_dbg", 1},
{"en_ch_evt_cnt", 1},
// TDC
{"dmon_sel", 5}, // NOTE: in online this is at the end of the header
{"dmon_sel_enable", 1}, // NOTE: in online this is at the end of the header
{"dmon_sw", 1}, // NOTE: in online this is at the end of the header
{"vnd2c_scale", 1},
{"vnd2c_offset", 2},
{"vnd2c", 6},
{"vncntbuffer_scale", 1},
{"vncntbuffer_offset", 2},
{"vncntbuffer", 6},
{"vncnt_scale", 1},
{"vncnt_offset", 2},
{"vncnt", 6},
{"vnpcp_scale", 1},
{"vnpcp_offset", 2},
{"vnpcp", 6},
{"vnvcodelay_scale", 1},
{"vnvcodelay_offset", 2},
{"vnvcodelay", 6},
{"vnvcobuffer_scale", 1},
{"vnvcobuffer_offset", 2},
{"vnvcobuffer", 6},
{"vnhitlogic_scale", 1},
{"vnhitlogic_offset", 2},
{"vnhitlogic", 6},
{"vnpfc_scale", 1},
{"vnpfc_offset", 2},
{"vnpfc", 6},
{"latchbias", 12},
// channel
{"energy_c_en", 1},
{"energy_r_en", 1},
{"sswitch", 1},
{"cm_sensing_high_r", 1},
{"amon_en_n", 1},
{"edge", 1},
{"edge_cml", 1},
{"cml_sc", 1},
{"tdctest_n", 1},
{"amonctrl", 3},
{"comp_spi", 2},
{"tthresh_offset_1", 1},
{"sipm", 6},
{"tthresh_offset_2", 1},
{"tthresh_sc", 2},
{"tthresh", 6},
{"ampcom_sc", 2},
{"ampcom", 6},
{"tthresh_offset_0", 1},
{"inputbias", 6},
{"ethresh", 8},
{"ebias", 3},
{"pole_sc", 1},
{"pole", 6},
{"cml", 4},
{"delay", 1},
{"pole_en_n", 1},
{"mask", 1},
{"recv_all", 1},
// footer
{"coin_xbar_lower_rx_ena", 1},
{"coin_xbar_lower_tx_ena", 1},
{"coin_xbar_lower_tx_vdac", 8},
{"coin_xbar_lower_tx_idac", 6},
{"coin_mat_xbl", 3},
{"coin_mat", 6}, // NOTE: in online this is in channels
{"coin_mat_xbu", 3},
{"coin_xbar_upper_rx_ena", 1},
{"coin_xbar_upper_tx_ena", 1},
{"coin_xbar_upper_tx_vdac", 8},
{"coin_xbar_upper_tx_idac", 6},
{"coin_wnd", 1},
{"amon_en", 1},
{"amon_dac", 8},
{"dmon_1_en", 1},
{"dmon_1_dac", 8},
{"dmon_2_en", 1},
{"dmon_2_dac", 8},
{"lvds_tx_vcm", 8},
{"lvds_tx_bias", 6}
}
},
{"Inverted",
{// header
{"gen_idle", true},
{"sync_ch_rst", true},
{"ext_trig_mode", true},
{"ext_trig_endtime_sign", true},
{"ext_trig_offset", false},
{"ext_trig_endtime", false},
{"ms_limits", false},
{"ms_switch_sel", true},
{"ms_debug", true},
{"tx_mode", false},
{"pll_setcoarse", true},
{"pll_envomonitor", true},
{"disable_coarse", true},
{"pll_lol_dbg", true},
{"en_ch_evt_cnt", true},
{"dmon_sel", true},
{"dmon_sel_enable", true},
{"dmon_sw", true},
// channel
{"energy_c_en", true},
{"energy_r_en", true},
{"sswitch", true},
{"cm_sensing_high_r", true},
{"amon_en_n", true},
{"edge", true},
{"edge_cml", true},
{"cml_sc", true},
{"tdctest_n", true},
{"amonctrl", true},
{"comp_spi", true},
{"tthresh_offset_1", true},
{"sipm", true},
{"tthresh_offset_2", true},
{"tthresh_sc", true},
{"tthresh", true},
{"ampcom_sc", true},
{"ampcom", true},
{"tthresh_offset_0", true},
{"inputbias", true},
{"ethresh", true},
{"ebias", true},
{"pole_sc", true},
{"pole", true},
{"cml", true},
{"delay", true},
{"pole_en_n", true},
{"mask", true},
{"recv_all", true},
// TDC
{"vnd2c_scale", true},
{"vnd2c_offset", true},
{"vnd2c", true},
{"vncntbuffer_scale", true},
{"vncntbuffer_offset",true},
{"vncntbuffer", true},
{"vncnt_scale", true},
{"vncnt_offset", true},
{"vncnt", true},
{"vnpcp_scale", true},
{"vnpcp_offset", true},
{"vnpcp", true},
{"vnvcodelay_scale", true},
{"vnvcodelay_offset", true},
{"vnvcodelay", true},
{"vnvcobuffer_scale", true},
{"vnvcobuffer_offset", true},
{"vnvcobuffer", true},
{"vnhitlogic_scale", true},
{"vnhitlogic_offset", true},
{"vnhitlogic", true},
{"vnpfc_scale", true},
{"vnpfc_offset", true},
{"vnpfc", true},
{"latchbias", false},
// footer
{"coin_xbar_lower_rx_ena", true},
{"coin_xbar_lower_tx_ena", true},
{"coin_xbar_lower_tx_vdac", true},
{"coin_xbar_lower_tx_idac", true},
{"coin_mat_xbl", true},
{"coin_mat", true},
{"coin_mat_xbu", true},
{"coin_xbar_upper_rx_ena", true},
{"coin_xbar_upper_tx_ena", true},
{"coin_xbar_upper_tx_vdac", true},
{"coin_xbar_upper_tx_idac", true},
{"coin_wnd", true},
{"amon_en", true},
{"amon_dac", true},
{"dmon_1_en", true},
{"dmon_1_dac", true},
{"dmon_2_en", true},
{"dmon_2_dac", true},
{"lvds_tx_vcm", true},
{"lvds_tx_bias", true}
}
}
}
}
};