File mupix_registers.h

/************************************************
 * Register map header file
 * Automatically generated from
 * /Users/mariuskoppel/mu3e/online/common/libmudaq/../../common/firmware/registers/mupix_registers.vhd
 * On 2025-07-07T10:27:21.135892
 ************************************************/

#ifndef MUPIX_REGISTERS__H
#define MUPIX_REGISTERS__H

#define BIAS_BIT 0
#define GET_BIAS_BIT(REG) ((REG >> 0) & 0x1)
#define SET_BIAS_BIT(REG) ((1 << 0) | REG)
#define UNSET_BIAS_BIT(REG) ((~(1 << 0)) & REG)
#define CONF_BIT 1
#define GET_CONF_BIT(REG) ((REG >> 1) & 0x1)
#define SET_CONF_BIT(REG) ((1 << 1) | REG)
#define UNSET_CONF_BIT(REG) ((~(1 << 1)) & REG)
#define VDAC_BIT 2
#define GET_VDAC_BIT(REG) ((REG >> 2) & 0x1)
#define SET_VDAC_BIT(REG) ((1 << 2) | REG)
#define UNSET_VDAC_BIT(REG) ((~(1 << 2)) & REG)
#define TDAC_BIT 3
#define GET_TDAC_BIT(REG) ((REG >> 3) & 0x1)
#define SET_TDAC_BIT(REG) ((1 << 3) | REG)
#define UNSET_TDAC_BIT(REG) ((~(1 << 3)) & REG)
#define MP_CTRL_COMBINED_START_REGISTER_W 0x0400
#define MP_CTRL_TDAC_START_REGISTER_W 0x0430
#define MP_CTRL_CHIP_SELECT1_REGISTER_W 0x0460
#define MP_CTRL_CHIP_SELECT2_REGISTER_W 0x0461
#define MP_CTRL_BIAS_REGISTER_W 0x0462
#define MP_CTRL_CONF_REGISTER_W 0x0463
#define MP_CTRL_VDAC_REGISTER_W 0x0464
#define MP_CTRL_SLOW_DOWN_REGISTER_W 0x0465
#define MP_CTRL_SPI_BUSY_REGISTER_R 0x0466
#define MP_CTRL_DIRECT_SPI_ENABLE_REGISTER_W 0x0467
#define MP_CTRL_SPI_ENABLE_REGISTER_W 0x0468
#define MP_CTRL_DIRECT_SPI_BUSY_REGISTER_R 0x0469
#define MP_CTRL_DIRECT_SPI_START_REGISTER_W 0x046a
#define MP_CTRL_DIRECT_SPI_CHIP_M_LOW_REGISTER_W 0x0480
#define MP_CTRL_DIRECT_SPI_CHIP_M_HIGH_REGISTER_W 0x0481
#define MP_CTRL_RESET_REGISTER_W 0x04a0
#define MP_CTRL_RUN_TEST_REGISTER_W 0x04a1
#define MP_CTRL_N_FREE_PAGES_REGISTER_R 0x04a2
#define MP_CTRL_TESTRAM_RDATA_REGISTER_R 0x04a3
#define MP_CTRL_TESTRAM_WADDR_REGISTER_W 0x04a4
#define MP_CTRL_TESTRAM_RADDR_REGISTER_W 0x04a5
#define MP_CTRL_TESTRAM_WDATA_REGISTER_W 0x04a6
#define MP_CTRL_SLOW_CLK_SHIFT_REGISTER_W 0x04a7
#define MP_CTRL_SIN_INVERT_REGISTER_W 0x04a8
#define MP_CTRL_PIXEL_ADDR_REGISTER0_W 0x04a9
#define MP_CTRL_PIXEL_ADDR_REGISTER1_W 0x04a9
#define MP_CTRL_EXT_CMD_START_REGISTER_W 0x0800
#define MP_READOUT_MODE_REGISTER_W 0x1300
#define INVERT_TS_BIT 0
#define GET_INVERT_TS_BIT(REG) ((REG >> 0) & 0x1)
#define SET_INVERT_TS_BIT(REG) ((1 << 0) | REG)
#define UNSET_INVERT_TS_BIT(REG) ((~(1 << 0)) & REG)
#define INVERT_TS2_BIT 1
#define GET_INVERT_TS2_BIT(REG) ((REG >> 1) & 0x1)
#define SET_INVERT_TS2_BIT(REG) ((1 << 1) | REG)
#define UNSET_INVERT_TS2_BIT(REG) ((~(1 << 1)) & REG)
#define GRAY_TS_BIT 2
#define GET_GRAY_TS_BIT(REG) ((REG >> 2) & 0x1)
#define SET_GRAY_TS_BIT(REG) ((1 << 2) | REG)
#define UNSET_GRAY_TS_BIT(REG) ((~(1 << 2)) & REG)
#define GRAY_TS2_BIT 3
#define GET_GRAY_TS2_BIT(REG) ((REG >> 3) & 0x1)
#define SET_GRAY_TS2_BIT(REG) ((1 << 3) | REG)
#define UNSET_GRAY_TS2_BIT(REG) ((~(1 << 3)) & REG)
#define CHIP_ID_MODE_RANGE_HI 5
#define CHIP_ID_MODE_RANGE_LOW 4
#define GET_CHIP_ID_MODE_RANGE(REG) ((REG >> 4) & 0x3)
#define SET_CHIP_ID_MODE_RANGE(REG, VAL) ((REG & (~(0x3 << 4))) | ((VAL & 0x3) << 4))
#define TOT_MODE_RANGE_HI 8
#define TOT_MODE_RANGE_LOW 6
#define GET_TOT_MODE_RANGE(REG) ((REG >> 6) & 0x7)
#define SET_TOT_MODE_RANGE(REG, VAL) ((REG & (~(0x7 << 6))) | ((VAL & 0x7) << 6))
#define RESET_COUNTERS_BIT 29
#define GET_RESET_COUNTERS_BIT(REG) ((REG >> 29) & 0x1)
#define SET_RESET_COUNTERS_BIT(REG) ((1 << 29) | REG)
#define UNSET_RESET_COUNTERS_BIT(REG) ((~(1 << 29)) & REG)
#define REJECT_PACKAGE_WITH_ERROR_BIT 30
#define GET_REJECT_PACKAGE_WITH_ERROR_BIT(REG) ((REG >> 30) & 0x1)
#define SET_REJECT_PACKAGE_WITH_ERROR_BIT(REG) ((1 << 30) | REG)
#define UNSET_REJECT_PACKAGE_WITH_ERROR_BIT(REG) ((~(1 << 30)) & REG)
#define SEND_LVDS_ERRORS_BIT 31
#define GET_SEND_LVDS_ERRORS_BIT(REG) ((REG >> 31) & 0x1)
#define SET_SEND_LVDS_ERRORS_BIT(REG) ((1 << 31) | REG)
#define UNSET_SEND_LVDS_ERRORS_BIT(REG) ((~(1 << 31)) & REG)
#define MP_LVDS_LINK_MASK_REGISTER_W 0x1301
#define MP_LVDS_LINK_MASK2_REGISTER_W 0x1302
#define MP_DATA_GEN_CONTROL_REGISTER_W 0x1303
#define MP_DATA_GEN_HIT_P_RANGE_HI 3
#define MP_DATA_GEN_HIT_P_RANGE_LOW 0
#define GET_MP_DATA_GEN_HIT_P_RANGE(REG) ((REG >> 0) & 0xf)
#define SET_MP_DATA_GEN_HIT_P_RANGE(REG, VAL) ((REG & (~(0xf << 0))) | ((VAL & 0xf) << 0))
#define MP_DATA_GEN_FULL_STEAM_BIT 4
#define GET_MP_DATA_GEN_FULL_STEAM_BIT(REG) ((REG >> 4) & 0x1)
#define SET_MP_DATA_GEN_FULL_STEAM_BIT(REG) ((1 << 4) | REG)
#define UNSET_MP_DATA_GEN_FULL_STEAM_BIT(REG) ((~(1 << 4)) & REG)
#define MP_DATA_GEN_SYNC_BIT 5
#define GET_MP_DATA_GEN_SYNC_BIT(REG) ((REG >> 5) & 0x1)
#define SET_MP_DATA_GEN_SYNC_BIT(REG) ((1 << 5) | REG)
#define UNSET_MP_DATA_GEN_SYNC_BIT(REG) ((~(1 << 5)) & REG)
#define MP_DATA_GEN_ENGAGE_BIT 16
#define GET_MP_DATA_GEN_ENGAGE_BIT(REG) ((REG >> 16) & 0x1)
#define SET_MP_DATA_GEN_ENGAGE_BIT(REG) ((1 << 16) | REG)
#define UNSET_MP_DATA_GEN_ENGAGE_BIT(REG) ((~(1 << 16)) & REG)
#define MP_DATA_GEN_SORT_IN_BIT 17
#define GET_MP_DATA_GEN_SORT_IN_BIT(REG) ((REG >> 17) & 0x1)
#define SET_MP_DATA_GEN_SORT_IN_BIT(REG) ((1 << 17) | REG)
#define UNSET_MP_DATA_GEN_SORT_IN_BIT(REG) ((~(1 << 17)) & REG)
#define MP_DATA_GEN_ENABLE_BIT 31
#define GET_MP_DATA_GEN_ENABLE_BIT(REG) ((REG >> 31) & 0x1)
#define SET_MP_DATA_GEN_ENABLE_BIT(REG) ((1 << 31) | REG)
#define UNSET_MP_DATA_GEN_ENABLE_BIT(REG) ((~(1 << 31)) & REG)
#define MP_DATA_BYPASS_SELECT_REGISTER_W 0x1305
#define MP_TS_HISTO_SELECT_REGISTER_W 0x1306
#define MP_TS_HISTO_LINK_SELECT_RANGE_HI 15
#define MP_TS_HISTO_LINK_SELECT_RANGE_LOW 0
#define GET_MP_TS_HISTO_LINK_SELECT_RANGE(REG) ((REG >> 0) & 0xffff)
#define SET_MP_TS_HISTO_LINK_SELECT_RANGE(REG, VAL) \
    ((REG & (~(0xffff << 0))) | ((VAL & 0xffff) << 0))
#define MP_TS_HISTO_N_SAMPLE_RANGE_HI 31
#define MP_TS_HISTO_N_SAMPLE_RANGE_LOW 16
#define GET_MP_TS_HISTO_N_SAMPLE_RANGE(REG) ((REG >> 16) & 0xffff)
#define SET_MP_TS_HISTO_N_SAMPLE_RANGE(REG, VAL) \
    ((REG & (~(0xffff << 16))) | ((VAL & 0xffff) << 16))
#define MP_LAST_SORTER_HIT_REGISTER_R 0x1307
#define MP_SORTER_INJECT_REGISTER_W 0x1308
#define MP_SORTER_INJECT_SELECT_RANGE_HI 7
#define MP_SORTER_INJECT_SELECT_RANGE_LOW 4
#define GET_MP_SORTER_INJECT_SELECT_RANGE(REG) ((REG >> 4) & 0xf)
#define SET_MP_SORTER_INJECT_SELECT_RANGE(REG, VAL) ((REG & (~(0xf << 4))) | ((VAL & 0xf) << 4))
#define MP_SORTER_INJECT_ENABLE_BIT 8
#define GET_MP_SORTER_INJECT_ENABLE_BIT(REG) ((REG >> 8) & 0x1)
#define SET_MP_SORTER_INJECT_ENABLE_BIT(REG) ((1 << 8) | REG)
#define UNSET_MP_SORTER_INJECT_ENABLE_BIT(REG) ((~(1 << 8)) & REG)
#define MP_CHIP_UNPACKER_CNT_REGISTER_R 0x1309
#define MP_CHIP_UNPACKER_CNT_REGISTER_W 0x130a
#define MP_CHIP_UNPACKER_CNT_SELECT_RANGE_HI 7
#define MP_CHIP_UNPACKER_CNT_SELECT_RANGE_LOW 0
#define GET_MP_CHIP_UNPACKER_CNT_SELECT_RANGE(REG) ((REG >> 0) & 0xff)
#define SET_MP_CHIP_UNPACKER_CNT_SELECT_RANGE(REG, VAL) \
    ((REG & (~(0xff << 0))) | ((VAL & 0xff) << 0))
#define MP_CNT_UNPACKER_SELECT_RANGE_HI 10
#define MP_CNT_UNPACKER_SELECT_RANGE_LOW 8
#define GET_MP_CNT_UNPACKER_SELECT_RANGE(REG) ((REG >> 8) & 0x7)
#define SET_MP_CNT_UNPACKER_SELECT_RANGE(REG, VAL) ((REG & (~(0x7 << 8))) | ((VAL & 0x7) << 8))
#define MP_HIT_ENA_CNT_SORTER_IN_REGISTER_R 0x130b
#define MP_HIT_ENA_CNT_SORTER_SELECT_REGISTER_W 0x130c
#define MP_HIT_ENA_CNT_SORTER_OUT_REGISTER_R 0x130d
#define MP_RESET_LVDS_N_REGISTER_W 0x130f
#define MP_USE_ARRIVAL_TIME1_REGISTER_W 0x1310
#define MP_USE_ARRIVAL_TIME2_REGISTER_W 0x1311
#define MP_TRIGGER0_REGISTER_R 0x1312
#define MP_TRIGGER1_REGISTER_R 0x1313
#define MP_TRIGGER0_REG_REGISTER_R 0x1314
#define MP_TRIGGER1_REG_REGISTER_R 0x1315
#define MP_LVDS_INVERT_0_REGISTER_W 0x1316
#define MP_LVDS_INVERT_1_REGISTER_W 0x1317
#define MP_IS_A_0_REGISTER_R 0x1318
#define MP_IS_A_1_REGISTER_R 0x1319
#define MP_IS_B_0_REGISTER_R 0x1320
#define MP_IS_B_1_REGISTER_R 0x1321
#define MP_IS_C_0_REGISTER_R 0x1322
#define MP_IS_C_1_REGISTER_R 0x1323
#define MP_READBACK_FIFOS_START_REGISTER_R 0x2000
#define MP_READBACK_MEMS_START_REGISTER_R 0x3000
#define MP_HIT_ARRIVAL_START_REGISTER_R 0x1200
#define MP_SORTER_COUNTER_REGISTER_R 0x1000
#define MP_SORTER_NINTIME_REGISTER_R 0x1000
#define MP_SORTER_NOUTOFTIME_REGISTER_R 0x100c
#define MP_SORTER_NOVERFLOW_REGISTER_R 0x1018
#define MP_SORTER_NOUT_REGISTER_R 0x1024
#define MP_SORTER_CREDIT_REGISTER_R 0x1025
#define MP_SORTER_DELAY_REGISTER_W 0x1028

#endif  // #ifndef MUPIX_REGISTERS__H