File feb_sc_registers.h

/************************************************
 * Register map header file
 * Automatically generated from
 * /Users/mariuskoppel/mu3e/online/common/libmudaq/../../common/firmware/registers/feb_sc_registers.vhd
 * On 2025-07-07T10:27:21.007422
 ************************************************/

#ifndef FEB_SC_REGISTERS__H
#define FEB_SC_REGISTERS__H

#define PACKET_TYPE_SC 0x7
#define PACKET_TYPE_SC_READ 0x0
#define PACKET_TYPE_SC_WRITE 0x1
#define PACKET_TYPE_SC_READ_NONINCREMENTING 0x2
#define PACKET_TYPE_SC_WRITE_NONINCREMENTING 0x3
#define PACKET_R_BIT_POSITION 24
#define GET_PACKET_R_BIT_POSITION(REG) ((REG >> 24) & 0x1)
#define SET_PACKET_R_BIT_POSITION(REG) ((1 << 24) | REG)
#define UNSET_PACKET_R_BIT_POSITION(REG) ((~(1 << 24)) & REG)
#define PACKET_T_BIT_POSITION 25
#define GET_PACKET_T_BIT_POSITION(REG) ((REG >> 25) & 0x1)
#define SET_PACKET_T_BIT_POSITION(REG) ((1 << 25) | REG)
#define UNSET_PACKET_T_BIT_POSITION(REG) ((~(1 << 25)) & REG)
#define PACKET_S_BIT_POSITION 26
#define GET_PACKET_S_BIT_POSITION(REG) ((REG >> 26) & 0x1)
#define SET_PACKET_S_BIT_POSITION(REG) ((1 << 26) | REG)
#define UNSET_PACKET_S_BIT_POSITION(REG) ((~(1 << 26)) & REG)
#define PACKET_M_BIT_POSITION 27
#define GET_PACKET_M_BIT_POSITION(REG) ((REG >> 27) & 0x1)
#define SET_PACKET_M_BIT_POSITION(REG) ((1 << 27) | REG)
#define UNSET_PACKET_M_BIT_POSITION(REG) ((~(1 << 27)) & REG)
#define STATUS_REGISTER_R 0xfc00
#define GIT_HASH_REGISTER_R 0xfc01
#define FPGA_TYPE_REGISTER_R 0xfc02
#define FPGA_ID_REGISTER_RW 0xfc03
#define CMD_LEN_REGISTER_RW 0xfc04
#define CMD_OFFSET_REGISTER_RW 0xfc05
#define RUN_STATE_RESET_BYPASS_REGISTER_RW 0xfc06
#define RUN_STATE_RANGE_HI 31
#define RUN_STATE_RANGE_LOW 16
#define GET_RUN_STATE_RANGE(REG) ((REG >> 16) & 0xffff)
#define SET_RUN_STATE_RANGE(REG, VAL) ((REG & (~(0xffff << 16))) | ((VAL & 0xffff) << 16))
#define RESET_BYPASS_RANGE_HI 7
#define RESET_BYPASS_RANGE_LOW 0
#define GET_RESET_BYPASS_RANGE(REG) ((REG >> 0) & 0xff)
#define SET_RESET_BYPASS_RANGE(REG, VAL) ((REG & (~(0xff << 0))) | ((VAL & 0xff) << 0))
#define RESET_BYPASS_BIT_REQUEST 8
#define GET_RESET_BYPASS_BIT_REQUEST(REG) ((REG >> 8) & 0x1)
#define SET_RESET_BYPASS_BIT_REQUEST(REG) ((1 << 8) | REG)
#define UNSET_RESET_BYPASS_BIT_REQUEST(REG) ((~(1 << 8)) & REG)
#define RESET_BYPASS_BIT_ENABLE 9
#define GET_RESET_BYPASS_BIT_ENABLE(REG) ((REG >> 9) & 0x1)
#define SET_RESET_BYPASS_BIT_ENABLE(REG) ((1 << 9) | REG)
#define UNSET_RESET_BYPASS_BIT_ENABLE(REG) ((~(1 << 9)) & REG)
#define RESET_PAYLOAD_REGISTER_RW 0xfc07
#define RESET_OPTICAL_LINKS_REGISTER_RW 0xfc08
#define RESET_PHASE_REGISTER_R 0xfc09
#define MERGER_RATE_REGISTER_R 0xfc0a
#define ARRIA_TEMP_REGISTER_RW 0xfc10
#define MAX10_ADC_0_1_REGISTER_R 0xfc11
#define MAX10_ADC_2_3_REGISTER_R 0xfc12
#define MAX10_ADC_4_5_REGISTER_R 0xfc13
#define MAX10_ADC_6_7_REGISTER_R 0xfc14
#define MAX10_ADC_8_9_REGISTER_R 0xfc15
#define FIREFLY_STATUS_REGISTER_R 0xfc16
#define FIREFLY1_INDEX_TEMP 0
#define FIREFLY1_INDEX_VOLT 1
#define FIREFLY1_INDEX_RX1_POW 2
#define FIREFLY1_INDEX_RX2_POW 3
#define FIREFLY1_INDEX_RX3_POW 4
#define FIREFLY1_INDEX_RX4_POW 5
#define FIREFLY1_INDEX_ALARM 6
#define FIREFLY2_INDEX_TEMP 7
#define FIREFLY2_INDEX_VOLT 8
#define FIREFLY2_INDEX_RX1_POW 9
#define FIREFLY2_INDEX_RX2_POW 10
#define FIREFLY2_INDEX_RX3_POW 11
#define FIREFLY2_INDEX_RX4_POW 12
#define FIREFLY2_INDEX_ALARM 13
#define NONINCREMENTING_TEST_REGISTER_RW 0xfc24
#define MAX10_VERSION_REGISTER_R 0xfc25
#define MAX10_STATUS_REGISTER_R 0xfc26
#define MAX10_STATUS_BIT_PLL_LOCKED 0
#define GET_MAX10_STATUS_BIT_PLL_LOCKED(REG) ((REG >> 0) & 0x1)
#define SET_MAX10_STATUS_BIT_PLL_LOCKED(REG) ((1 << 0) | REG)
#define UNSET_MAX10_STATUS_BIT_PLL_LOCKED(REG) ((~(1 << 0)) & REG)
#define MAX10_STATUS_BIT_SPI_ARRIA_CLK 1
#define GET_MAX10_STATUS_BIT_SPI_ARRIA_CLK(REG) ((REG >> 1) & 0x1)
#define SET_MAX10_STATUS_BIT_SPI_ARRIA_CLK(REG) ((1 << 1) | REG)
#define UNSET_MAX10_STATUS_BIT_SPI_ARRIA_CLK(REG) ((~(1 << 1)) & REG)
#define PROGRAMMING_CTRL_REGISTER_W 0xfc27
#define PROGRAMMING_STATUS_REGISTER_R 0xfc28
#define PROGRAMMING_STATUS_BIT_SPI_BUSY 1
#define GET_PROGRAMMING_STATUS_BIT_SPI_BUSY(REG) ((REG >> 1) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_SPI_BUSY(REG) ((1 << 1) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_SPI_BUSY(REG) ((~(1 << 1)) & REG)
#define PROGRAMMING_STATUS_BIT_FIFO_EMPTY 14
#define GET_PROGRAMMING_STATUS_BIT_FIFO_EMPTY(REG) ((REG >> 14) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_FIFO_EMPTY(REG) ((1 << 14) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_FIFO_EMPTY(REG) ((~(1 << 14)) & REG)
#define PROGRAMMING_STATUS_BIT_FIFO_FULL 15
#define GET_PROGRAMMING_STATUS_BIT_FIFO_FULL(REG) ((REG >> 15) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_FIFO_FULL(REG) ((1 << 15) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_FIFO_FULL(REG) ((~(1 << 15)) & REG)
#define PROGRAMMING_STATUS_BIT_CONF_DONE 16
#define GET_PROGRAMMING_STATUS_BIT_CONF_DONE(REG) ((REG >> 16) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_CONF_DONE(REG) ((1 << 16) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_CONF_DONE(REG) ((~(1 << 16)) & REG)
#define PROGRAMMING_STATUS_BIT_NSTATUS 17
#define GET_PROGRAMMING_STATUS_BIT_NSTATUS(REG) ((REG >> 17) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_NSTATUS(REG) ((1 << 17) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_NSTATUS(REG) ((~(1 << 17)) & REG)
#define PROGRAMMING_STATUS_BIT_TIMEOUT 18
#define GET_PROGRAMMING_STATUS_BIT_TIMEOUT(REG) ((REG >> 18) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_TIMEOUT(REG) ((1 << 18) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_TIMEOUT(REG) ((~(1 << 18)) & REG)
#define PROGRAMMING_STATUS_BIT_CRCERROR 19
#define GET_PROGRAMMING_STATUS_BIT_CRCERROR(REG) ((REG >> 19) & 0x1)
#define SET_PROGRAMMING_STATUS_BIT_CRCERROR(REG) ((1 << 19) | REG)
#define UNSET_PROGRAMMING_STATUS_BIT_CRCERROR(REG) ((~(1 << 19)) & REG)
#define PROGRAMMING_ADDR_REGISTER_W 0xfc29
#define PROGRAMMING_DATA_REGISTER_W 0xfc2a
#define REBOOT_REGISTER_RW 0xfc2d
#define SHUTDOWN_REGISTER_RW 0xfc2e
#define RUN_START_DENIAL_REGISTER_R 0xfc2f
#define RUN_NUMBER_REGISTER_R 0xfc2f
#define FIREFLY_XCVR_CH_SEL_REGISTER_RW 0xff00
#define FIREFLY_XCVR_N_CH_REGISTER_R 0xff01
#define FIREFLY_XCVR_CH_WIDTH_REGISTER_R 0xff02
#define FIREFLY_XCVR_TX_RESET_REGISTER_RW 0xff10
#define FIREFLY_XCVR_TX_STATUS_REGISTER_R 0xff11
#define FIREFLY_XCVR_TX_ERROR_REGISTER_R 0xff12
#define FIREFLY_XCVR_RX_RESET_REGISTER_RW 0xff20
#define FIREFLY_XCVR_RX_STATUS_REGISTER_R 0xff21
#define FIREFLY_XCVR_RX_ERROR_REGISTER_R 0xff22
#define FIREFLY_XCVR_LOL_REGISTER_R 0xff23
#define FIREFLY_XCVR_ERR_CNT_REGISTER_R 0xff24
#define FIREFLY_XCVR_DATA_REGISTER_R 0xff2a
#define FIREFLY_XCVR_DATAK_REGISTER_R 0xff2b
#define FIREFLY_XCVR_GBIT_REGISTER_R 0xff2c
#define FIREFLY_XCVR_LOOPBACK_REGISTER_RW 0xff2f
#define RESET_LINK_RESTART_REGISTER_RW 0xff30
#define LVDS_CONTROLLER_STATE_REGISTER_R 0xff31

#endif  // #ifndef FEB_SC_REGISTERS__H